git-svn-id: http://moon:8086/svn/vhdl/trunk@1418 cc03376c-175c-47c8-b038-4cd826a8556b
1182 lines
29 KiB
VHDL
1182 lines
29 KiB
VHDL
-------------------------------------------------------------------------
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-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
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-- This file: loadable ROM
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--
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-- Copyright (C) 2007 J. Ahrensfeld
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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-- For questions and ideas, please contact the author at jens@jayfield.org
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--
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--------------------------------------------------------------------------
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LIBRARY ieee;
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use IEEE.STD_LOGIC_1164.ALL;
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USE ieee.numeric_std.ALL;
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library UNISIM;
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use UNISIM.VComponents.all;
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library work;
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use work.cpu_pkg.all;
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ENTITY irom IS
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Port (
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clk : in STD_LOGIC;
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ce : in STD_LOGIC;
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addr : in inst_addr_t;
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dout : out inst_t
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);
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END irom;
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ARCHITECTURE loadable OF irom IS
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-- JASM_ROM_INSERT_HERE
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-- Assembled from main.jsm
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type imem_rom_t is array (0 to 1023) of inst_t;
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signal imem_rom : imem_rom_t :=
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(
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"110000" & X"002", -- 0x000: JMP 0x002
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"111111" & X"000", -- 0x001: RETI
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"101000" & X"0B0", -- 0x002: XIN R00, (0x0B)
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"100100" & X"010", -- 0x003: XOUT (0x01), R00
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"011001" & X"010", -- 0x004: AND R00, 0x01
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"110001" & X"002", -- 0x005: JZ 0x002
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"101000" & X"0B0", -- 0x006: XIN R00, (0x0B)
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"100100" & X"010", -- 0x007: XOUT (0x01), R00
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"111011" & X"06E", -- 0x008: CALL 0x06E
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"111011" & X"055", -- 0x009: CALL 0x055
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"000011" & X"000", -- 0x00A: MOV R00, 0x00
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"000011" & X"001", -- 0x00B: MOV R01, 0x00
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"111011" & X"05A", -- 0x00C: CALL 0x05A
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"111011" & X"074", -- 0x00D: CALL 0x074
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"000011" & X"030", -- 0x00E: MOV R00, 0x03
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"111011" & X"06B", -- 0x00F: CALL 0x06B
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"101001" & X"000", -- 0x010: CIN R00, (0x00)
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"010001" & X"300", -- 0x011: ADD R00, 0x30
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"111011" & X"05E", -- 0x012: CALL 0x05E
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"000011" & X"000", -- 0x013: MOV R00, 0x00
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"111011" & X"061", -- 0x014: CALL 0x061
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"111011" & X"074", -- 0x015: CALL 0x074
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"111011" & X"074", -- 0x016: CALL 0x074
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"000011" & X"0D0", -- 0x017: MOV R00, 0x0D
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"111011" & X"06B", -- 0x018: CALL 0x06B
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"111011" & X"07B", -- 0x019: CALL 0x07B
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"000011" & X"000", -- 0x01A: MOV R00, 0x00
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"000011" & X"031", -- 0x01B: MOV R01, 0x03
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"111011" & X"05A", -- 0x01C: CALL 0x05A
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"000011" & X"160", -- 0x01D: MOV R00, 0x16
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"111011" & X"06B", -- 0x01E: CALL 0x06B
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"111011" & X"074", -- 0x01F: CALL 0x074
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"000011" & X"000", -- 0x020: MOV R00, 0x00
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"000011" & X"0A1", -- 0x021: MOV R01, 0x0A
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"111011" & X"05A", -- 0x022: CALL 0x05A
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"000011" & X"A0F", -- 0x023: MOV R15, 0xA0
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"001111" & X"00F", -- 0x024: TST R15
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"110001" & X"02F", -- 0x025: JZ 0x02F
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"010101" & X"01F", -- 0x026: DEC R15
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"000011" & X"301", -- 0x027: MOV R01, 0x30
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"001111" & X"3A1", -- 0x028: CMP R01, 0x3A
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"111001" & X"02E", -- 0x029: JEQ 0x02E
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"000010" & X"010", -- 0x02A: MOV R00, R01
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"010001" & X"011", -- 0x02B: INC R01
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"111011" & X"05E", -- 0x02C: CALL 0x05E
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"110000" & X"028", -- 0x02D: JMP 0x028
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"110000" & X"024", -- 0x02E: JMP 0x024
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"111011" & X"074", -- 0x02F: CALL 0x074
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"000011" & X"000", -- 0x030: MOV R00, 0x00
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"000011" & X"0C1", -- 0x031: MOV R01, 0x0C
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"111011" & X"05A", -- 0x032: CALL 0x05A
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"111011" & X"050", -- 0x033: CALL 0x050
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"000011" & X"000", -- 0x034: MOV R00, 0x00
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"000011" & X"1E1", -- 0x035: MOV R01, 0x1E
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"111011" & X"05A", -- 0x036: CALL 0x05A
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"000011" & X"0D0", -- 0x037: MOV R00, 0x0D
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"111011" & X"06B", -- 0x038: CALL 0x06B
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"111011" & X"07B", -- 0x039: CALL 0x07B
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"000011" & X"0D0", -- 0x03A: MOV R00, 0x0D
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"111011" & X"06B", -- 0x03B: CALL 0x06B
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"111011" & X"07B", -- 0x03C: CALL 0x07B
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"000011" & X"0D0", -- 0x03D: MOV R00, 0x0D
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"111011" & X"06B", -- 0x03E: CALL 0x06B
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"111011" & X"07B", -- 0x03F: CALL 0x07B
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"000011" & X"0D0", -- 0x040: MOV R00, 0x0D
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"111011" & X"06B", -- 0x041: CALL 0x06B
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"111011" & X"07B", -- 0x042: CALL 0x07B
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"000011" & X"0D0", -- 0x043: MOV R00, 0x0D
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"111011" & X"06B", -- 0x044: CALL 0x06B
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"111011" & X"07B", -- 0x045: CALL 0x07B
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"000011" & X"0D0", -- 0x046: MOV R00, 0x0D
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"111011" & X"06B", -- 0x047: CALL 0x06B
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"111011" & X"07B", -- 0x048: CALL 0x07B
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"000011" & X"0D0", -- 0x049: MOV R00, 0x0D
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"111011" & X"06B", -- 0x04A: CALL 0x06B
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"111011" & X"07B", -- 0x04B: CALL 0x07B
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"000011" & X"0D0", -- 0x04C: MOV R00, 0x0D
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"111011" & X"06B", -- 0x04D: CALL 0x06B
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"111011" & X"074", -- 0x04E: CALL 0x074
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"110000" & X"008", -- 0x04F: JMP 0x008
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"111100" & X"000", -- 0x050: PUSH R00
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"000011" & X"020", -- 0x051: MOV R00, 0x02
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"100100" & X"0B0", -- 0x052: XOUT (0x0B), R00
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"111101" & X"000", -- 0x053: POP R00
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"111110" & X"000", -- 0x054: RET
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"111100" & X"000", -- 0x055: PUSH R00
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"000011" & X"010", -- 0x056: MOV R00, 0x01
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"100100" & X"0B0", -- 0x057: XOUT (0x0B), R00
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"111101" & X"000", -- 0x058: POP R00
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"111110" & X"000", -- 0x059: RET
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"111011" & X"06E", -- 0x05A: CALL 0x06E
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"100100" & X"091", -- 0x05B: XOUT (0x09), R01
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"100100" & X"080", -- 0x05C: XOUT (0x08), R00
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"111110" & X"000", -- 0x05D: RET
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"111011" & X"06E", -- 0x05E: CALL 0x06E
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"100100" & X"0A0", -- 0x05F: XOUT (0x0A), R00
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"111110" & X"000", -- 0x060: RET
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"111100" & X"001", -- 0x061: PUSH R01
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"000010" & X"001", -- 0x062: MOV R01, R00
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"000100" & X"010", -- 0x063: MOVX R00, (R01)
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"010001" & X"011", -- 0x064: INC R01
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"001111" & X"000", -- 0x065: TST R00
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"110001" & X"069", -- 0x066: JZ 0x069
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"111011" & X"05E", -- 0x067: CALL 0x05E
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"110000" & X"063", -- 0x068: JMP 0x063
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"111101" & X"001", -- 0x069: POP R01
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"111110" & X"000", -- 0x06A: RET
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"111011" & X"050", -- 0x06B: CALL 0x050
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"111011" & X"061", -- 0x06C: CALL 0x061
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"111110" & X"000", -- 0x06D: RET
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"111100" & X"000", -- 0x06E: PUSH R00
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"101000" & X"0B0", -- 0x06F: XIN R00, (0x0B)
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"011001" & X"020", -- 0x070: AND R00, 0x02
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"110001" & X"06F", -- 0x071: JZ 0x06F
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"111101" & X"000", -- 0x072: POP R00
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"111110" & X"000", -- 0x073: RET
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"111100" & X"00F", -- 0x074: PUSH R15
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"000011" & X"0AF", -- 0x075: MOV R15, 0x0A
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"111011" & X"07B", -- 0x076: CALL 0x07B
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"010101" & X"01F", -- 0x077: DEC R15
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"110010" & X"076", -- 0x078: JNZ 0x076
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"111101" & X"00F", -- 0x079: POP R15
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"111110" & X"000", -- 0x07A: RET
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"111100" & X"00F", -- 0x07B: PUSH R15
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"000011" & X"0AF", -- 0x07C: MOV R15, 0x0A
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"111011" & X"082", -- 0x07D: CALL 0x082
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"010101" & X"01F", -- 0x07E: DEC R15
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"110010" & X"07D", -- 0x07F: JNZ 0x07D
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"111101" & X"00F", -- 0x080: POP R15
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"111110" & X"000", -- 0x081: RET
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"111100" & X"00F", -- 0x082: PUSH R15
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"000011" & X"0AF", -- 0x083: MOV R15, 0x0A
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"111011" & X"089", -- 0x084: CALL 0x089
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"010101" & X"01F", -- 0x085: DEC R15
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"110010" & X"084", -- 0x086: JNZ 0x084
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"111101" & X"00F", -- 0x087: POP R15
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"111110" & X"000", -- 0x088: RET
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"111100" & X"00F", -- 0x089: PUSH R15
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"000011" & X"0AF", -- 0x08A: MOV R15, 0x0A
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"111011" & X"090", -- 0x08B: CALL 0x090
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"010101" & X"01F", -- 0x08C: DEC R15
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"110010" & X"08B", -- 0x08D: JNZ 0x08B
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"111101" & X"00F", -- 0x08E: POP R15
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"111110" & X"000", -- 0x08F: RET
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"111100" & X"00F", -- 0x090: PUSH R15
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"000011" & X"0AF", -- 0x091: MOV R15, 0x0A
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"111011" & X"097", -- 0x092: CALL 0x097
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"010101" & X"01F", -- 0x093: DEC R15
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"110010" & X"092", -- 0x094: JNZ 0x092
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"111101" & X"00F", -- 0x095: POP R15
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"111110" & X"000", -- 0x096: RET
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"111100" & X"00F", -- 0x097: PUSH R15
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"000011" & X"63F", -- 0x098: MOV R15, 0x63
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"000000" & X"000", -- 0x099: NOP
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"000000" & X"000", -- 0x09A: NOP
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"000000" & X"000", -- 0x09B: NOP
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"010101" & X"01F", -- 0x09C: DEC R15
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"110010" & X"099", -- 0x09D: JNZ 0x099
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"111101" & X"00F", -- 0x09E: POP R15
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"111110" & X"000", -- 0x09F: RET
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"111100" & X"00F", -- 0x0A0: PUSH R15
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"000011" & X"09F", -- 0x0A1: MOV R15, 0x09
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"000000" & X"000", -- 0x0A2: NOP
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"000000" & X"000", -- 0x0A3: NOP
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"000000" & X"000", -- 0x0A4: NOP
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"010101" & X"01F", -- 0x0A5: DEC R15
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"110010" & X"0A2", -- 0x0A6: JNZ 0x0A2
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"111101" & X"00F", -- 0x0A7: POP R15
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"111110" & X"000", -- 0x0A8: RET
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"000000" & X"000",
|
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"000000" & X"000",
|
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"000000" & X"000",
|
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"000000" & X"000",
|
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"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
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|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000"
|
|
);
|
|
|
|
signal jtag_ld_clk : STD_LOGIC;
|
|
signal jtag_ld_we : STD_LOGIC;
|
|
signal jtag_ld_addr : inst_addr_t;
|
|
signal jtag_ld_dout : inst_t;
|
|
signal jtag_ld_din : inst_t;
|
|
signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
|
|
signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
|
|
signal user_regi, user_rego : unsigned (31 downto 0);
|
|
constant id : unsigned (31 downto 0) := X"BABE" & X"BEEF";
|
|
|
|
begin
|
|
|
|
--------------------------------------------------------------------------
|
|
-- Virtex-4: JTAG Loader
|
|
--------------------------------------------------------------------------
|
|
i00_BUFG : BUFG
|
|
port map
|
|
(
|
|
O => bs_clk1,
|
|
I => bs_clk0
|
|
);
|
|
|
|
i01_BUFG : BUFG
|
|
port map
|
|
(
|
|
O => bs_update1,
|
|
I => bs_update0
|
|
);
|
|
|
|
BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4
|
|
generic map
|
|
(
|
|
JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
|
|
)
|
|
port map
|
|
(
|
|
CAPTURE => bs_capture, -- CAPTURE output from TAP controller
|
|
DRCK => bs_clk0, -- Data register output for USER functions
|
|
RESET => bs_rst, -- Reset output from TAP controller
|
|
SEL => bs_sel, -- USER active output
|
|
SHIFT => bs_shift, -- SHIFT output from TAP controller
|
|
TDI => bs_tdi, -- TDI output from TAP controller
|
|
UPDATE => bs_update0, -- UPDATE output from TAP controller
|
|
TDO => bs_tdo -- Data input for USER function
|
|
);
|
|
|
|
jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-inst_addr_t'length+1);
|
|
jtag_ld_din <= user_regi(inst_t'length-1 downto 0);
|
|
jtag_ld_clk <= bs_update1;
|
|
jtag_ld_we <= bs_sel;
|
|
|
|
sipo:
|
|
process (bs_rst, bs_clk1, bs_tdi, bs_shift)
|
|
begin
|
|
if bs_rst = '1' then
|
|
user_regi <= (others => '0');
|
|
elsif rising_edge(bs_clk1) then
|
|
if bs_shift = '1' then
|
|
user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
piso:
|
|
process (bs_rst, bs_clk1, bs_shift, user_rego)
|
|
begin
|
|
bs_tdo <= user_rego(0);
|
|
if bs_rst = '1' then
|
|
user_rego <= (others => '0');
|
|
elsif rising_edge(bs_clk1) then
|
|
if bs_shift = '1' then
|
|
user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
|
|
else
|
|
user_rego <= (user_rego'left downto inst_t'length => '0') & jtag_ld_dout;
|
|
-- user_rego <= id;
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
--------------------------------------------------------------------------
|
|
-- ROM Read/Write
|
|
--------------------------------------------------------------------------
|
|
PROM_READ:
|
|
process(clk, ce)
|
|
begin
|
|
if rising_edge(clk) and ce = '1' then
|
|
dout <= imem_rom(to_integer(addr));
|
|
end if;
|
|
end process;
|
|
|
|
PROM_WRITE:
|
|
process(jtag_ld_clk, jtag_ld_we)
|
|
begin
|
|
if rising_edge(jtag_ld_clk) then
|
|
if jtag_ld_we = '1' then
|
|
imem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
|
|
else
|
|
jtag_ld_dout <= imem_rom(to_integer(jtag_ld_addr));
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
--------------------------------------------------------------------------
|
|
end loadable;
|