1436 lines
86 KiB
Templ
1436 lines
86 KiB
Templ
$ version 1.1
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# Signals in packages :
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# Signals in entities :
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/tb_mips_top/debug
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/tb_mips_top/tb_fin
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/tb_mips_top/nmi
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/tb_mips_top/rst
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/tb_mips_top/clk
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/tb_mips_top/eb
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/tb_mips_top/ack_i
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/tb_mips_top/srdy_i
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/tb_mips_top/addr_o
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/tb_mips_top/dat_i
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/tb_mips_top/dat_o
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/tb_mips_top/we_o
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/tb_mips_top/sel_o
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/tb_mips_top/cyc_o
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/tb_mips_top/stb_o
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/tb_mips_top/mrdy_o
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/tb_mips_top/int
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/tb_mips_top/cyc_i_rom
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/tb_mips_top/ack_o_rom
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/tb_mips_top/srdy_o_rom
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/tb_mips_top/dat_o_rom
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/tb_mips_top/cyc_i_flash
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/tb_mips_top/ack_o_flash
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/tb_mips_top/srdy_o_flash
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/tb_mips_top/dat_o_flash
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/tb_mips_top/cyc_i_sram
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/tb_mips_top/ack_o_sram
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/tb_mips_top/srdy_o_sram
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/tb_mips_top/dat_o_sram
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/tb_mips_top/cyc_i_gpio
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/tb_mips_top/ack_o_gpio
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/tb_mips_top/srdy_o_gpio
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/tb_mips_top/dat_o_gpio
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/tb_mips_top/cyc_i_uart
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/tb_mips_top/ack_o_uart
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/tb_mips_top/srdy_o_uart
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/tb_mips_top/dat_o_uart
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/tb_mips_top/flash_cs_n
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/tb_mips_top/flash_we_n
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/tb_mips_top/flash_oe_n
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/tb_mips_top/flash_be_n
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/tb_mips_top/sram_cs_n
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/tb_mips_top/sram_be_n
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/tb_mips_top/sram_wr_n
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/tb_mips_top/sram_oe_n
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/tb_mips_top/sram_a
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/tb_mips_top/sram_d
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/tb_mips_top/flash_a
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/tb_mips_top/flash_d
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/tb_mips_top/flash_page_mode_en
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/tb_mips_top/gpi_0
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/tb_mips_top/gpo_0
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/tb_mips_top/int_timer
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/tb_mips_top/int_uart
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/tb_mips_top/rx
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/tb_mips_top/tx
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/tb_mips_top/mem_area
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/tb_mips_top/sram_data
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/tb_mips_top/flash_data
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/tb_mips_top/uut/debug
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/tb_mips_top/uut/eb
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/tb_mips_top/uut/nmi
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/tb_mips_top/uut/cpu_clk
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/tb_mips_top/uut/rst_i
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/tb_mips_top/uut/clk_i
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/tb_mips_top/uut/ack_i
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/tb_mips_top/uut/srdy_i
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/tb_mips_top/uut/addr_o
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/tb_mips_top/uut/dat_i
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/tb_mips_top/uut/dat_o
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/tb_mips_top/uut/we_o
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/tb_mips_top/uut/sel_o
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/tb_mips_top/uut/cyc_o
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/tb_mips_top/uut/stb_o
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/tb_mips_top/uut/mrdy_o
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/tb_mips_top/uut/int
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/tb_mips_top/uut/imem_err
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/tb_mips_top/uut/dmem_err
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/tb_mips_top/uut/biu_busy
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/tb_mips_top/uut/biu_rst
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/tb_mips_top/uut/cpu_rst
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/tb_mips_top/uut/cpu_run
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/tb_mips_top/uut/pipe_cop_ir
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/tb_mips_top/uut/pipe_cop_ir_en
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/tb_mips_top/uut/pipe_cop_din
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/tb_mips_top/uut/pipe_cop_dout
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/tb_mips_top/uut/pipe_ctrl_in
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/tb_mips_top/uut/pipe_ctrl_out
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/tb_mips_top/uut/cop0_ctrl_in
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/tb_mips_top/uut/cop0_ctrl_out
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/tb_mips_top/uut/biu_ctrl_in
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/tb_mips_top/uut/biu_ctrl_out
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/tb_mips_top/uut/inst_pipeline/rst
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/tb_mips_top/uut/inst_pipeline/clk
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/tb_mips_top/uut/inst_pipeline/ce
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/tb_mips_top/uut/inst_pipeline/imem_err
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/tb_mips_top/uut/inst_pipeline/dmem_err
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/tb_mips_top/uut/inst_pipeline/cop_ir
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/tb_mips_top/uut/inst_pipeline/cop_ir_en
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/tb_mips_top/uut/inst_pipeline/cop_din
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/tb_mips_top/uut/inst_pipeline/cop_dout
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/tb_mips_top/uut/inst_pipeline/ctrl_out
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/tb_mips_top/uut/inst_pipeline/ctrl_in
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/tb_mips_top/uut/inst_pipeline/dtlb_qry_out
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/tb_mips_top/uut/inst_pipeline/dtlb_qry_in
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/tb_mips_top/uut/inst_pipeline/dcache_qry_out
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/tb_mips_top/uut/inst_pipeline/dcache_qry_in
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/tb_mips_top/uut/inst_pipeline/itlb_qry_out
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/tb_mips_top/uut/inst_pipeline/itlb_qry_in
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/tb_mips_top/uut/inst_pipeline/icache_qry_out
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/tb_mips_top/uut/inst_pipeline/icache_qry_in
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/tb_mips_top/uut/inst_pipeline/id_stage
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/tb_mips_top/uut/inst_pipeline/ex_stage
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/tb_mips_top/uut/inst_pipeline/mem_stage
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/tb_mips_top/uut/inst_pipeline/wb_stage
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/tb_mips_top/uut/inst_pipeline/clk_2
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/tb_mips_top/uut/inst_pipeline/clk_1
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/tb_mips_top/uut/inst_pipeline/hdu
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/tb_mips_top/uut/inst_pipeline/sdu
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/tb_mips_top/uut/inst_pipeline/reg_a
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/tb_mips_top/uut/inst_pipeline/reg_b
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/tb_mips_top/uut/inst_pipeline/branch_ce
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/tb_mips_top/uut/inst_pipeline/cpu_run
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/tb_mips_top/uut/inst_pipeline/alu_result
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/tb_mips_top/uut/inst_pipeline/mul_result
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/tb_mips_top/uut/inst_pipeline/mul_busy
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/tb_mips_top/uut/inst_pipeline/ex_events_instr
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/tb_mips_top/uut/inst_pipeline/ex_events_alu
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/tb_mips_top/uut/inst_pipeline/ex_events_mem
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/tb_mips_top/uut/inst_pipeline/ex_events_dtlb
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/tb_mips_top/uut/inst_pipeline/ex_events
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/tb_mips_top/uut/inst_pipeline/mem_events
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/tb_mips_top/uut/inst_pipeline/stage_rst
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/tb_mips_top/uut/inst_pipeline/pipe_rst
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/tb_mips_top/uut/inst_pipeline/pc
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/tb_mips_top/uut/inst_pipeline/inst_muldiv/rst
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/tb_mips_top/uut/inst_pipeline/inst_muldiv/clk
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/tb_mips_top/uut/inst_pipeline/inst_muldiv/hilo_we
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/tb_mips_top/uut/inst_pipeline/inst_muldiv/din_hi
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/tb_mips_top/uut/inst_pipeline/inst_muldiv/din_lo
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/tb_mips_top/uut/inst_pipeline/inst_muldiv/mul_divn
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/tb_mips_top/uut/inst_pipeline/inst_muldiv/start
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/tb_mips_top/uut/inst_pipeline/inst_muldiv/s_un
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/tb_mips_top/uut/inst_pipeline/inst_muldiv/hilo_sel
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/tb_mips_top/uut/inst_pipeline/inst_muldiv/busy
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/tb_mips_top/uut/inst_pipeline/inst_muldiv/dout
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/tb_mips_top/uut/inst_pipeline/inst_muldiv/pprod
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/tb_mips_top/uut/inst_pipeline/inst_muldiv/sign1
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/tb_mips_top/uut/inst_pipeline/inst_muldiv/sign2
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/tb_mips_top/uut/inst_pipeline/inst_muldiv/s1_r
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/tb_mips_top/uut/inst_pipeline/inst_muldiv/s2_r
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/tb_mips_top/uut/inst_pipeline/inst_muldiv/sr_r
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/tb_mips_top/uut/inst_pipeline/inst_muldiv/cy
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/tb_mips_top/uut/inst_pipeline/inst_muldiv/mul_start
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/tb_mips_top/uut/inst_pipeline/inst_muldiv/mul_en
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/tb_mips_top/uut/inst_pipeline/inst_muldiv/sum_en
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/tb_mips_top/uut/inst_pipeline/inst_muldiv/pre_sum_vld
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/tb_mips_top/uut/inst_pipeline/inst_muldiv/pp_reg
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/tb_mips_top/uut/inst_pipeline/inst_muldiv/pre_const
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/tb_mips_top/uut/inst_pipeline/inst_muldiv/result
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/tb_mips_top/uut/inst_pipeline/inst_muldiv/add_op1
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/tb_mips_top/uut/inst_pipeline/inst_muldiv/add_op2
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/tb_mips_top/uut/inst_pipeline/inst_muldiv/add_res
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/tb_mips_top/uut/inst_pipeline/inst_muldiv/ppadd_op1
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/tb_mips_top/uut/inst_pipeline/inst_muldiv/ppadd_op2
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/tb_mips_top/uut/inst_pipeline/inst_muldiv/ppadd_res
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/tb_mips_top/uut/inst_pipeline/inst_muldiv/ppadd_cyi
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/tb_mips_top/uut/inst_pipeline/inst_muldiv/ppadd_cyo
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/tb_mips_top/uut/inst_pipeline/inst_muldiv/pp_op1_r
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/tb_mips_top/uut/inst_pipeline/inst_muldiv/pp_op1
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/tb_mips_top/uut/inst_pipeline/inst_muldiv/pp_op2
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/tb_mips_top/uut/inst_pipeline/inst_muldiv/pp_op2_r
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/tb_mips_top/uut/inst_pipeline/inst_muldiv/bsy
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/tb_mips_top/uut/inst_pipeline/inst_muldiv/div_add_res
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/tb_mips_top/uut/inst_pipeline/inst_muldiv/div_add_op1
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/tb_mips_top/uut/inst_pipeline/inst_muldiv/div_add_op2
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/tb_mips_top/uut/inst_pipeline/inst_muldiv/div_add_cyi
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/tb_mips_top/uut/inst_pipeline/inst_muldiv/div_qbit
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/tb_mips_top/uut/inst_pipeline/inst_muldiv/div_start
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/tb_mips_top/uut/inst_pipeline/inst_muldiv/div_en
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/tb_mips_top/uut/inst_pipeline/inst_muldiv/div_a
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/tb_mips_top/uut/inst_pipeline/inst_muldiv/div_m
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/tb_mips_top/uut/inst_pipeline/inst_muldiv/div_m_n
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/tb_mips_top/uut/inst_pipeline/inst_muldiv/div_q
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/tb_mips_top/uut/inst_pipeline/inst_muldiv/s
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/tb_mips_top/uut/inst_pipeline/inst_muldiv/sn
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/tb_mips_top/uut/inst_pipeline/inst_muldiv/cycle_cnt
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/tb_mips_top/uut/inst_pipeline/inst_muldiv/cycle_cnt_preset
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/tb_mips_top/uut/inst_pipeline/inst_muldiv/cycle_cnt_load
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/tb_mips_top/uut/inst_pipeline/inst_muldiv/div_fin_en
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/tb_mips_top/uut/inst_pipeline/inst_bcu_alt_id/op1_in
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/tb_mips_top/uut/inst_pipeline/inst_bcu_alt_id/op2_in
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/tb_mips_top/uut/inst_pipeline/inst_bcu_alt_id/flags
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/tb_mips_top/uut/inst_pipeline/inst_bcu_alt_ex/op1_in
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/tb_mips_top/uut/inst_pipeline/inst_bcu_alt_ex/op2_in
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/tb_mips_top/uut/inst_pipeline/inst_bcu_alt_ex/flags
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/tb_mips_top/uut/inst_pipeline/inst_reg_dual/clk_w
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/tb_mips_top/uut/inst_pipeline/inst_reg_dual/we
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/tb_mips_top/uut/inst_pipeline/inst_reg_dual/en
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/tb_mips_top/uut/inst_pipeline/inst_reg_dual/wptr
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/tb_mips_top/uut/inst_pipeline/inst_reg_dual/din
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/tb_mips_top/uut/inst_pipeline/inst_reg_dual/rptr_a
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/tb_mips_top/uut/inst_pipeline/inst_reg_dual/rptr_b
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/tb_mips_top/uut/inst_pipeline/inst_reg_dual/dout_a
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/tb_mips_top/uut/inst_pipeline/inst_reg_dual/dout_b
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/tb_mips_top/uut/inst_pipeline/inst_reg_dual/reg_mem
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/tb_mips_top/uut/inst_pipeline/inst_shifter/shift_ctrl
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/tb_mips_top/uut/inst_pipeline/inst_shifter/din
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/tb_mips_top/uut/inst_pipeline/inst_shifter/dout
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/tb_mips_top/uut/inst_pipeline/inst_shifter/rot_data
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/tb_mips_top/uut/inst_pipeline/inst_shifter/sa_rnd
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/tb_mips_top/uut/inst_pipeline/inst_shifter/fill
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/tb_mips_top/uut/inst_pipeline/inst_shifter/fill_mask
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/tb_mips_top/uut/inst_pipeline/inst_shifter/fill_mask_addr
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/tb_mips_top/uut/inst_pipeline/inst_shifter/dout_filled
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/tb_mips_top/uut/inst_pipeline/inst_alu/op1_in
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/tb_mips_top/uut/inst_pipeline/inst_alu/op2_in
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/tb_mips_top/uut/inst_pipeline/inst_alu/op2_shifted
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/tb_mips_top/uut/inst_pipeline/inst_alu/ctrl
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/tb_mips_top/uut/inst_pipeline/inst_alu/result
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/tb_mips_top/uut/inst_pipeline/inst_alu/flags
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/tb_mips_top/uut/inst_pipeline/inst_alu/sum_res
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/tb_mips_top/uut/inst_pipeline/inst_alu/and_res
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/tb_mips_top/uut/inst_pipeline/inst_alu/xor_res
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/tb_mips_top/uut/inst_pipeline/inst_alu/nor_res
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/tb_mips_top/uut/inst_pipeline/inst_alu/or_res
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/tb_mips_top/uut/inst_pipeline/inst_alu/eq
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/tb_mips_top/uut/inst_pipeline/inst_alu/sa
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/tb_mips_top/uut/inst_pipeline/inst_alu/sb
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/tb_mips_top/uut/inst_pipeline/inst_alu/sr
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/tb_mips_top/uut/inst_pipeline/inst_alu/c
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/tb_mips_top/uut/inst_pipeline/inst_alu/lts
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/tb_mips_top/uut/inst_pipeline/inst_alu/ltu
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/tb_mips_top/uut/inst_cop/rst
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/tb_mips_top/uut/inst_cop/clk
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/tb_mips_top/uut/inst_cop/eb
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/tb_mips_top/uut/inst_cop/int
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/tb_mips_top/uut/inst_cop/nmi
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/tb_mips_top/uut/inst_cop/ir_en
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/tb_mips_top/uut/inst_cop/ir
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/tb_mips_top/uut/inst_cop/ctrl_in
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/tb_mips_top/uut/inst_cop/ctrl_out
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/tb_mips_top/uut/inst_cop/din
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/tb_mips_top/uut/inst_cop/dout
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/tb_mips_top/uut/inst_cop/regs
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/tb_mips_top/uut/inst_cop/ex_reg_we
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/tb_mips_top/uut/inst_cop/index
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/tb_mips_top/uut/inst_cop/random
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/tb_mips_top/uut/inst_cop/ptebase
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/tb_mips_top/uut/inst_cop/itlb_exc
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/tb_mips_top/uut/inst_cop/dtlb_exc
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/tb_mips_top/uut/inst_cop/itlb_entry_hi
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/tb_mips_top/uut/inst_cop/itlb_entry_lo
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/tb_mips_top/uut/inst_cop/dtlb_entry_hi
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/tb_mips_top/uut/inst_cop/dtlb_entry_lo
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/tb_mips_top/uut/inst_cop/entry_hi
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/tb_mips_top/uut/inst_cop/entry_lo
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/tb_mips_top/uut/inst_cop/exc_code
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/tb_mips_top/uut/inst_cop/tlb_sel
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/tb_mips_top/uut/inst_cop/epc_reg_we
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/tb_mips_top/uut/inst_cop/code_reg_we
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/tb_mips_top/uut/inst_cop/bd
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/tb_mips_top/uut/inst_cop/sw_int
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/tb_mips_top/uut/inst_cop/ip_reg
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/tb_mips_top/uut/inst_cop/im_reg
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/tb_mips_top/uut/inst_cop/status_save
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/tb_mips_top/uut/inst_cop/status_rest
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/tb_mips_top/uut/inst_cop/eflags
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/tb_mips_top/uut/inst_cop/eb_reg
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/tb_mips_top/uut/inst_cop/icache_info
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/tb_mips_top/uut/inst_cop/dcache_info
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/tb_mips_top/uut/inst_cop/reg_rptr
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/tb_mips_top/uut/inst_cop/reg_wptr
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/tb_mips_top/uut/inst_cop/inject_exc
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/tb_mips_top/uut/inst_cop/latch_vect_en
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/tb_mips_top/uut/inst_cop/int_nmi
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/tb_mips_top/uut/inst_cop/nmi_asserted
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/tb_mips_top/uut/inst_cop/cop_pipe_id
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/tb_mips_top/uut/inst_cop/cop_pipe_ex
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/tb_mips_top/uut/inst_cop/exc_state
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/tb_mips_top/uut/inst_cop/exc_staten
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/tb_mips_top/uut/inst_biu/clk
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/tb_mips_top/uut/inst_biu/busy
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/tb_mips_top/uut/inst_biu/imem_err
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/tb_mips_top/uut/inst_biu/dmem_err
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/tb_mips_top/uut/inst_biu/rst_i
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/tb_mips_top/uut/inst_biu/clk_i
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/tb_mips_top/uut/inst_biu/ack_i
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/tb_mips_top/uut/inst_biu/srdy_i
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/tb_mips_top/uut/inst_biu/addr_o
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/tb_mips_top/uut/inst_biu/mdat_i
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/tb_mips_top/uut/inst_biu/mdat_o
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/tb_mips_top/uut/inst_biu/we_o
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/tb_mips_top/uut/inst_biu/sel_o
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/tb_mips_top/uut/inst_biu/cyc_o
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/tb_mips_top/uut/inst_biu/stb_o
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/tb_mips_top/uut/inst_biu/mrdy_o
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/tb_mips_top/uut/inst_biu/ctrl_in
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/tb_mips_top/uut/inst_biu/ctrl_out
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