jens ef9b538769 - fir_stage_sys only uses pipe_latency as parameter ...

git-svn-id: http://moon:8086/svn/vhdl/trunk@235 cc03376c-175c-47c8-b038-4cd826a8556b

2009-01-13 09:29:45 +00:00

..

ac97_ctrl

- Intital revision

2008-11-01 21:48:26 +00:00

CPUs

- added Tpd to 'dout' for sim

2008-11-05 09:34:56 +00:00

FIFO

- Bugfix: changed 'ptr_r' from 'bcnt_r' to 'bnxt_r' to prevent read delay when FIFO is read (re = 1)

2008-10-25 11:21:47 +00:00

filter

- fir_stage_sys only uses pipe_latency as parameter

2009-01-13 09:29:45 +00:00

fix_std

Initial import

2008-08-23 08:20:30 +00:00

fixed

deleted

2009-01-11 15:31:42 +00:00

fixed_ja

Initial import

2008-08-23 08:20:30 +00:00

jasm

Initial import

2008-08-23 08:20:30 +00:00

misc

Initial version

2009-01-12 10:11:09 +00:00

PCK_FIO-1.16

Initial import

2008-08-23 08:20:30 +00:00

PCK_FIO-2002.7

Initial import

2008-08-23 08:20:30 +00:00

radio

- fir_stage_sys only uses pipe_latency as parameter

2009-01-13 09:29:45 +00:00

SDRAM

- Cleaned up

2008-10-26 23:36:00 +00:00

SSRAM

- Using MODELSIM_HOME environment variable

2008-10-23 21:21:24 +00:00

uart

Intital revision

2008-10-10 21:31:24 +00:00

VGA_ctrl

- removed delay at color output. Fixes image problems.

2008-10-25 20:11:03 +00:00