jens
e5a31bdf7c
Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/branches/BRANCH_MIPS_TLB@1010 cc03376c-175c-47c8-b038-4cd826a8556b
162 lines
3.5 KiB
VHDL
162 lines
3.5 KiB
VHDL
LIBRARY ieee;
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use IEEE.STD_LOGIC_1164.ALL;
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USE ieee.numeric_std.ALL;
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library work;
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use work.mips_types.all;
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use work.mips_util_pkg.all;
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ENTITY tb_cam IS
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END tb_cam;
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ARCHITECTURE behavior OF tb_cam IS
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constant CLK_PERIOD : time := 10 ns;
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constant DATA_WIDTH : integer := 20;
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constant CAM_NUM_ENTRIES : integer := 32;
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signal CLK_O : std_logic := '1';
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signal RST_O : std_logic := '1';
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signal cam_we : std_logic := '0';
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signal cam_re : std_logic := '0';
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signal cam_vld : std_logic := '0';
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signal cam_rdy : std_logic := '-';
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signal cam_addr : unsigned(lg2(CAM_NUM_ENTRIES)-1 downto 0) := (others => '0');
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signal cam_data : unsigned(DATA_WIDTH-1 downto 0) := (others => '0');
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signal cam_hit : unsigned (CAM_NUM_ENTRIES-1 downto 0);
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signal cam_hit_vld : std_logic := '-';
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BEGIN
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inst_cam: entity work.cam
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GENERIC MAP
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(
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NUM_ENTRIES => CAM_NUM_ENTRIES,
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DATA_WIDTH => DATA_WIDTH,
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CAM_RAM_MAX_WIDTH => 15
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)
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PORT MAP
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(
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rst => RST_O,
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clk => CLK_O,
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rdy => cam_rdy,
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re => cam_re,
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we => cam_we,
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vld => cam_vld,
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addr => cam_addr,
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din => cam_data,
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hit => cam_hit,
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hit_vld => cam_hit_vld
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);
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CLK_GEN: process
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begin
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wait for CLK_PERIOD/2;
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CLK_O <= not CLK_O;
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end process;
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STIMULUS: process
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variable result : unsigned(31 downto 0);
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procedure cam_entry_write(index : integer; data : unsigned; valid : std_logic) is
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begin
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cam_data <= data;
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cam_addr <= to_unsigned(index, lg2(CAM_NUM_ENTRIES));
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cam_vld <= valid;
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cam_we <= '1';
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wait until rising_edge(CLK_O) and cam_rdy = '1';
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cam_we <= '0';
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end procedure cam_entry_write;
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procedure cam_lookup(data : unsigned) is
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begin
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cam_data <= data;
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cam_re <= '1';
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wait until rising_edge(CLK_O) and cam_rdy = '1';
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cam_re <= '0';
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end procedure cam_lookup;
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begin
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wait for 6*CLK_PERIOD;
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RST_O <= '0';
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wait for 60*CLK_PERIOD;
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wait until rising_edge(CLK_O) and cam_rdy = '1';
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cam_entry_write(1, X"CAFE_1", '1');
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cam_entry_write(2, X"CAFE_2", '1');
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wait for 8*CLK_PERIOD;
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wait until rising_edge(CLK_O) and cam_rdy = '1';
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cam_lookup(X"CAFE_1");
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cam_lookup(X"CAFE_2");
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wait for 8*CLK_PERIOD;
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wait until rising_edge(CLK_O) and cam_rdy = '1';
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-- overwrite
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cam_entry_write(2, X"BEEF_2", '1');
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wait for 8*CLK_PERIOD;
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wait until rising_edge(CLK_O) and cam_rdy = '1';
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-- overwrite entry
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cam_entry_write(2, X"CAFE_2", '1');
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-- new entry
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cam_entry_write(3, X"CAFE_3", '1');
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cam_entry_write(4, X"CAFE_4", '1');
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wait for 8*CLK_PERIOD;
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wait until rising_edge(CLK_O) and cam_rdy = '1';
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cam_entry_write(1, X"CAFE_1", '0');
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cam_entry_write(2, X"CAFE_2", '0');
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cam_entry_write(3, X"CAFE_3", '0');
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cam_entry_write(4, X"CAFE_4", '0');
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wait for 8*CLK_PERIOD;
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wait until rising_edge(CLK_O) and cam_rdy = '1';
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cam_lookup(X"BEEF_2");
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cam_lookup(X"CAFE_1");
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cam_lookup(X"CAFE_2");
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cam_lookup(X"CAFE_3");
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cam_lookup(X"CAFE_4");
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wait for 8*CLK_PERIOD;
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wait until rising_edge(CLK_O) and cam_rdy = '1';
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cam_entry_write(1, X"CAFE_1", '1');
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cam_entry_write(2, X"CAFE_2", '1');
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cam_entry_write(3, X"CAFE_3", '1');
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cam_entry_write(4, X"CAFE_4", '1');
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wait for 8*CLK_PERIOD;
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wait until rising_edge(CLK_O) and cam_rdy = '1';
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cam_lookup(X"CAFE_1");
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cam_lookup(X"CAFE_2");
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cam_lookup(X"CAFE_3");
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cam_lookup(X"CAFE_4");
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wait for 8*CLK_PERIOD;
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wait until rising_edge(CLK_O) and cam_rdy = '1';
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cam_entry_write(7, X"CAFE_7", '0');
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wait for 8*CLK_PERIOD;
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wait until rising_edge(CLK_O) and cam_rdy = '1';
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wait;
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end process;
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END;
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