jens
67d79572d7
git-svn-id: http://moon:8086/svn/vhdl/trunk@1411 cc03376c-175c-47c8-b038-4cd826a8556b
142 lines
3.5 KiB
VHDL
142 lines
3.5 KiB
VHDL
--------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 17:16:42 13.05.2007
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-- Design Name: tb_nco
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-- Module Name: tb_nco.vhd
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-- Project Name: nco
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.MATH_REAL.ALL;
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USE ieee.numeric_std.ALL;
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use std.textio.all; -- Imports the standard textio package.
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library ieee_proposed;
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use ieee_proposed.math_utility_pkg.all;
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use ieee_proposed.fixed_pkg.all;
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library work;
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use work.fixed_util_pkg.all;
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use work.filter_pkg.all;
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use work.fir_pkg.all;
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ENTITY syn_fir_lowpass IS
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Generic
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(
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ntaps_per_stage : integer := 32;
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nstages : integer := 2;
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nbits_in : integer := 16;
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nbits_in_frac : integer := 14;
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nbits_stages : integer := 32;
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nbits_stages_frac : integer := 30;
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nbits_out : integer := 32;
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nbits_out_frac : integer := 30;
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fir_npipe_regs : integer := 7
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);
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PORT(
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rst : in std_logic;
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clk : in std_logic;
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h_addr : in natural range 0 to nstages*ntaps_per_stage-1;
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h_we : in std_logic;
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h_din : in signed(nbits_stages-1 downto 0);
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start_i : in std_logic;
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ready_i : out std_logic;
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x_valid_i : in std_logic;
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x_din_i : in signed(nbits_in-1 downto 0);
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y_valid_i : out std_logic;
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y_dout_i : out signed(nbits_out-1 downto 0);
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start_q : in std_logic;
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ready_q : out std_logic;
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x_valid_q : in std_logic;
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x_din_q : in signed(nbits_in-1 downto 0);
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y_valid_q : out std_logic;
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y_dout_q : out signed(nbits_out-1 downto 0)
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);
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END syn_fir_lowpass;
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ARCHITECTURE behavior OF syn_fir_lowpass IS
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-- Lowpass parameter
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--Outputs
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SIGNAL h_i, h_q : sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac));
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SIGNAL x_i, x_q : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
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SIGNAL y_i, y_q : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
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SIGNAL h_in : sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac));
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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inst_fir_semi_parallel_i : entity work.fir_semi_parallel
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GENERIC MAP
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(
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ntaps_per_stage => ntaps_per_stage,
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nstages => nstages,
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pipe_latency => fir_npipe_regs,
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nbits_in => nbits_in,
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nbits_in_frac => nbits_in_frac,
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nbits_stages => nbits_stages,
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nbits_stages_frac => nbits_stages_frac,
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nbits_out => nbits_out,
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nbits_out_frac => nbits_out_frac
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)
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PORT MAP
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(
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rst => rst,
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clk => clk,
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h_addr => h_addr,
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h_we => h_we,
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h_in => h_in,
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din_vld => x_valid_i,
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din => x_i,
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dout_vld => y_valid_i,
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start => start_i,
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rdy => ready_i,
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dout => y_i
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);
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inst_fir_semi_parallel_q : entity work.fir_semi_parallel
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GENERIC MAP
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(
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ntaps_per_stage => ntaps_per_stage,
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nstages => nstages,
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pipe_latency => fir_npipe_regs,
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nbits_in => nbits_in,
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nbits_in_frac => nbits_in_frac,
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nbits_stages => nbits_stages,
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nbits_stages_frac => nbits_stages_frac,
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nbits_out => nbits_out,
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nbits_out_frac => nbits_out_frac
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)
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PORT MAP
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(
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rst => rst,
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clk => clk,
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h_addr => h_addr,
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h_we => h_we,
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h_in => h_in,
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din_vld => x_valid_q,
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din => x_q,
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dout_vld => y_valid_q,
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start => start_q,
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rdy => ready_q,
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dout => y_q
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);
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h_in <= sfixed(h_din);
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x_i <= sfixed(x_din_i);
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y_dout_i <= signed(y_i);
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x_q <= sfixed(x_din_q);
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y_dout_q <= signed(y_q);
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END;
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