78 lines
1.9 KiB
VHDL
78 lines
1.9 KiB
VHDL
-----------------------------------------------------------------------
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-- $Header: /tmp/cvsroot/VHDL/lib/misc/hpi_port.vhd,v 1.1 2008-09-04 17:48:15 Jens Exp $
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-----------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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------------------------------------------------------------------
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entity hpi_port is
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Port (
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rst : in std_logic;
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clk : in std_logic;
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we : in std_logic;
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din : in unsigned(31 downto 0);
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dout : out unsigned(31 downto 0);
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hpi_d : inout unsigned(15 downto 0);
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hpi_a : out unsigned(1 downto 0);
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hpi_csn : out std_logic;
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hpi_wrn : out std_logic;
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hpi_rdn : out std_logic
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);
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end hpi_port;
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architecture Behavioral of hpi_port is
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type hpi_t is record
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d : unsigned(15 downto 0);
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a : unsigned(1 downto 0);
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cs : std_logic;
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wr : std_logic;
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rd : std_logic;
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drive_d : std_logic;
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end record;
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------------------------------------------------------------------
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begin
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proc_lcd_port:
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process(rst, clk)
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variable vhpi : hpi_t;
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begin
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if (rst = '1') then
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dout <= (others => '0');
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vhpi.d := (others => '0');
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vhpi.a := (others => '0');
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vhpi.cs := '0';
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vhpi.wr := '0';
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vhpi.rd := '0';
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vhpi.drive_d := '0';
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elsif rising_edge(clk) then
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dout <= X"0000" & hpi_d;
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if we = '1' then
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vhpi.d := din(15 downto 0);
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vhpi.a := din(17 downto 16);
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vhpi.cs := din(18);
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vhpi.wr := din(19);
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vhpi.rd := din(20);
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vhpi.drive_d := din(21);
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end if;
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end if;
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if vhpi.cs = '1' then
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hpi_a <= vhpi.a;
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else
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hpi_a <= (others => 'Z');
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end if;
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if vhpi.drive_d = '1' and vhpi.rd = '0' then
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hpi_d <= vhpi.d;
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else
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hpi_d <= (others => 'Z');
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end if;
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hpi_csn <= not vhpi.cs;
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hpi_wrn <= not vhpi.wr;
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hpi_rdn <= not vhpi.rd;
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end process;
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------------------------------------------------------------------
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end Behavioral;
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