jens
4fe3a1c636
- uses ieee_proposed.fixed_pkg git-svn-id: http://moon:8086/svn/vhdl/trunk@167 cc03376c-175c-47c8-b038-4cd826a8556b
82 lines
1.9 KiB
VHDL
82 lines
1.9 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 12:16:14 10/02/05
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-- Design Name:
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-- Module Name: cordic_stage_pre - Behavioral
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-- Project Name:
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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--------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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library ieee_proposed;
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use ieee_proposed.math_utility_pkg.all;
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use ieee_proposed.fixed_pkg.all;
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library work;
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use work.fixed_util_pkg.all;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity cic_i_pipe is
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Generic
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(
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max_width : integer := 32;
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max_width_frac : integer := 20
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);
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Port
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(
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clk : in std_logic;
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rst : in std_logic;
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vld_in : in std_logic;
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din : in sfixed;
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dout : out sfixed;
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vld_out : out std_logic
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);
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end cic_i_pipe;
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architecture Behavioral of cic_i_pipe is
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signal accu : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
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------------------------------------------------------------
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begin
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dout <= resize(accu, shi(max_width, max_width_frac), slo(max_width, max_width_frac));
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------------------------------------------------------------
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integ_proc:
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process(clk)
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variable x : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
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begin
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if rising_edge(clk) then
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vld_out <= '0';
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if rst = '1' then
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accu <= (shi(max_width, max_width_frac) downto slo(max_width, max_width_frac) => '0');
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elsif vld_in = '1' then
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vld_out <= '1';
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x := resize(din, x);
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accu <= resize(x + accu, accu);
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end if;
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end if;
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end process;
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------------------------------------------------------------
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end Behavioral;
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