jens dcea9c36b7 - Quick and dirty hack: ...

avoid buscycle to finish even if data available,
  caused by latency of async-FIFO empty flag

Committed on the Free edition of March Hare Software CVSNT Server.
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git-svn-id: http://moon:8086/svn/vhdl/trunk@996 cc03376c-175c-47c8-b038-4cd826a8556b

2013-08-04 17:58:37 +00:00

..

ac97_ctrl

Initial revision

2013-02-07 14:50:03 +00:00

CPUs

- added MMU

2013-07-28 19:54:13 +00:00

emac

- uses now new generic DPRAMs

2013-02-09 09:26:12 +00:00

FIFO

- FIFOs only use registered output DPRAMs

2013-02-09 10:42:07 +00:00

filter

- renamed fifo_*sync_ctrl

2009-01-30 21:30:21 +00:00

fix_std

Initial import

2008-08-23 08:20:30 +00:00

fixed

deleted

2009-01-11 15:31:42 +00:00

fixed_ja

Initial import

2008-08-23 08:20:30 +00:00

jasm

Initial import

2008-08-23 08:20:30 +00:00

JBUS

- Quick and dirty hack:

2013-08-04 17:58:37 +00:00

misc

- added WE_I for rom

2013-07-28 19:51:40 +00:00

PCK_FIO-1.16

Minor changes

2010-03-12 07:35:21 +00:00

PCK_FIO-2002.7

Initial import

2008-08-23 08:20:30 +00:00

ps2_port

- fixed rounding issue in usec prescaler

2010-02-09 11:46:08 +00:00

radio

Minor changes

2010-03-12 07:41:31 +00:00

rams

Initial revision

2013-02-09 09:27:21 +00:00

SDRAM

- uses now new generic DPRAMs

2013-02-09 10:45:59 +00:00

SSRAM

- Using MODELSIM_HOME environment variable

2008-10-23 21:21:24 +00:00

uart

- modified uart_status in simulation mode. Good for debugging.

2013-07-28 19:53:15 +00:00

VGA_ctrl

- cleaned up

2013-05-12 17:03:18 +00:00