122 lines
3.0 KiB
VHDL
122 lines
3.0 KiB
VHDL
-------------------------------------------------------------------------
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-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
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-- This file: Dual-ported register file with asynchrous read
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-- Copyright (C) 2007 J. Ahrensfeld
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-- This library is free software; you can redistribute it and/or
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-- modify it under the terms of the GNU Lesser General Public
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-- License as published by the Free Software Foundation; either
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-- version 2.1 of the License, or (at your option) any later version.
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-- This library is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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-- Lesser General Public License for more details.
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-- You should have received a copy of the GNU Lesser General Public
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-- License along with this library; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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-- For questions and ideas, please contact the author at jens@jayfield.org
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-----------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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use work.vga_types.all;
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entity linefifo is
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Generic
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(
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depth : natural := 64;
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almost_full_thresh : natural := 60;
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almost_empty_thresh : natural := 4
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);
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Port
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(
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rst : in STD_LOGIC;
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clk_w : in STD_LOGIC;
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clk_r : in STD_LOGIC;
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we_w : in STD_LOGIC;
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re_r : in STD_LOGIC;
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fifo_full : out STD_LOGIC;
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fifo_empty : out STD_LOGIC;
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fifo_afull : out STD_LOGIC;
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fifo_aempty : out STD_LOGIC;
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color_w : in color_t;
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color_r : out color_t
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);
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end linefifo;
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architecture Behavioral of linefifo is
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constant data_width : integer := 8;
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constant addr_width : integer := NextExpBaseTwo(depth);
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signal buf_we_w : STD_LOGIC;
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signal ptr_w : unsigned (ADDR_WIDTH-1 downto 0);
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signal ptr_r : unsigned (ADDR_WIDTH-1 downto 0);
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signal full : STD_LOGIC;
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signal empty : STD_LOGIC;
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signal almost_full : STD_LOGIC;
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signal almost_empty : STD_LOGIC;
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begin
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buf_we_w <= we_w;
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fifo_full <= full;
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fifo_empty <= empty;
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fifo_afull <= almost_full;
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fifo_aempty <= almost_empty;
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gen_line:
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for c in color_range_t generate
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begin
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inst_dpram: entity work.dpram
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GENERIC MAP
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(
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addr_width => addr_width,
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data_width => data_width
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)
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PORT MAP(
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clka => clk_w,
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clkb => clk_r,
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en_a => '1',
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en_b => '1',
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we_a => buf_we_w,
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addr_a => ptr_w,
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addr_b => ptr_r,
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din_a => color_w(c),
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dout_b => color_r(c)
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);
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end generate;
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inst_fifo_ctrl: entity work.async_fifo_ctrl
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GENERIC MAP
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(
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addr_width => ADDR_WIDTH,
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almost_full_thresh => almost_full_thresh,
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almost_empty_thresh => almost_empty_thresh
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)
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PORT MAP
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(
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rst => rst,
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clk_w => clk_w,
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clk_r => clk_r,
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we => we_w,
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re => re_r,
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ptr_w => ptr_w,
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ptr_r => ptr_r,
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fifo_full => full,
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fifo_empty => empty,
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fifo_afull => almost_full,
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fifo_aempty => almost_empty
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);
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end Behavioral;
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