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vhdl/projects/mips_sys/ise101/mips_sys/mips_sys_map.mrp
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jens 943e7e9388 update 
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git-svn-id: http://moon:8086/svn/vhdl/trunk@754 cc03376c-175c-47c8-b038-4cd826a8556b
2010-02-14 17:28:14 +00:00

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Release 10.1.03 Map K.39 (nt)
Xilinx Mapping Report File for Design 'mips_sys'
Design Information
------------------
Command Line : map -ise W:/vhdl/projects/mips_sys/ise101/mips_sys/mips_sys.ise -intstyle ise -p xc4vsx35-ff668-10
-timing -logic_opt on -ol high -xe n -t 1 -register_duplication -global_opt on -retiming on -equivalent_register_removal
on -cm area -pr b -k 4 -power off -o mips_sys_map.ncd mips_sys.ngd mips_sys.pcf
Target Device : xc4vsx35
Target Package : ff668
Target Speed : -10
Stepping Level : ES
Mapper Version : virtex4 -- $Revision: 1.4 $
Mapped Date : Sun Feb 14 18:06:35 2010
Design Summary
--------------
Number of errors: 0
Number of warnings: 68
Logic Utilization:
Number of Slice Flip Flops: 5,411 out of 30,720 17%
Number of 4 input LUTs: 8,647 out of 30,720 28%
Logic Distribution:
Number of occupied Slices: 6,008 out of 15,360 39%
Number of Slices containing only related logic: 6,008 out of 6,008 100%
Number of Slices containing unrelated logic: 0 out of 6,008 0%
*See NOTES below for an explanation of the effects of unrelated logic.
Total Number of 4 input LUTs: 9,036 out of 30,720 29%
Number used as logic: 7,647
Number used as a route-thru: 389
Number used as 16x1 RAMs: 6
Number used for Dual Port RAMs: 792
(Two LUTs used per Dual Port RAM)
Number used as Shift registers: 202
Number of bonded IOBs: 226 out of 448 50%
IOB Flip Flops: 350
IOB Dual-Data Rate Flops: 42
Number of BUFG/BUFGCTRLs: 12 out of 32 37%
Number used as BUFGs: 12
Number of FIFO16/RAMB16s: 51 out of 192 26%
Number used as RAMB16s: 51
Number of DCM_ADVs: 4 out of 8 50%
Number of BSCAN_VIRTEX4s: 1 out of 4 25%
Peak Memory Usage: 533 MB
Total REAL time to MAP completion: 8 mins 4 secs
Total CPU time to MAP completion: 7 mins 55 secs
Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report
Section 12 - Configuration String Information
Section 13 - Control Set Information
Section 14 - Utilization by Hierarchy
Section 1 - Errors
------------------
Section 2 - Warnings
--------------------
WARNING:LIT:421 - DIB0 should be connected if WRITE_WIDTH_B is set to 18 (RAMB16
symbol "inst_mips_top/inst_biu/inst_icache/inst_tag_ram/Mram_RAM1").
WARNING:LIT:243 - Logical network sys_usb_d_15_IOBUF/N2 has no load.
WARNING:LIT:395 - The above warning message base_net_load_rule is repeated 167
more times for the following (max. 5 shown):
sys_usb_d_15_IOBUF/N3,
sys_usb_d_14_IOBUF/N2,
sys_usb_d_14_IOBUF/N3,
sys_usb_d_13_IOBUF/N2,
sys_usb_d_13_IOBUF/N3
To see the details of these warning messages, please use the -detail switch.
WARNING:Pack:2549 - The register
"inst_uart_wb_1/inst_uart_tx/kcuart/pipeline_serial" has the property
IOB=TRUE, but was not packed into the OLOGIC component. The output signal for
register symbol inst_uart_wb_1/inst_uart_tx/kcuart/pipeline_serial requires
general routing.
WARNING:Pack:2549 - The register
"inst_uart_wb_1/inst_uart_tx/kcuart/pipeline_serial" has the property
IOB=TRUE, but was not packed into the OLOGIC component. The output signal for
register symbol inst_uart_wb_1/inst_uart_tx/kcuart/pipeline_serial requires
general routing.
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_1" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_765".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_2" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_763".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_3" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_761".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_4" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_759".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_5" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_757".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_6" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_755".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_7" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_753".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_8" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_751".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_9" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_749".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_10" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_747".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_11" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_745".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_12" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_743".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_13" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_741".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_21" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_725".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_14" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_739".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_22" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_723".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_23" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_721".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_15" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_737".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_31" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_705".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_24" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_719".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_16" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_735".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_32" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_703".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_25" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_717".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_17" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_733".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_18" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_731".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_26" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_715".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_19" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_729".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_27" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_713".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_20" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_727".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_28" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_711".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_29" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_709".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_30" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_707".
WARNING:Pack:2549 - The register "inst_ps2_wb_0/inst_ps2_core/ps2_data_tx" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal "inst_ps2_wb_0/inst_ps2_core/data_tx2" does not match the
ILOGIC SR signal "inst_ps2_phy_0/Inst_debounce_data/output_and0000".
WARNING:Pack:2549 - The register "inst_ps2_wb_0/inst_ps2_core/ps2_data_tx_1" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal "inst_ps2_wb_0/inst_ps2_core/data_tx2" does not match the
ILOGIC SR signal "inst_ps2_phy_0/Inst_debounce_data/output_and0000".
WARNING:Pack:2549 - The register "inst_ps2_wb_1/inst_ps2_core/ps2_data_tx" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal "inst_ps2_wb_1/inst_ps2_core/data_tx2" does not match the
ILOGIC SR signal "inst_ps2_phy_1/Inst_debounce_data/output_and0000".
WARNING:Pack:2549 - The register "inst_ps2_wb_1/inst_ps2_core/ps2_data_tx_1" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal "inst_ps2_wb_1/inst_ps2_core/data_tx2" does not match the
ILOGIC SR signal "inst_ps2_phy_1/Inst_debounce_data/output_and0000".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/dqs_zen_0_4" has
the property IOB=TRUE, but was not packed into the OLOGIC component. Register
inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/dqs_zen_0_4
set/reset disagrees with another register in the OLOGIC component.
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/dqs_zen_0_3" has
the property IOB=TRUE, but was not packed into the OLOGIC component. Register
inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/dqs_zen_0_3
set/reset disagrees with another register in the OLOGIC component.
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/dqs_zen_0_2" has
the property IOB=TRUE, but was not packed into the OLOGIC component. Register
inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/dqs_zen_0_2
set/reset disagrees with another register in the OLOGIC component.
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/dqs_zen_0_1" has
the property IOB=TRUE, but was not packed into the OLOGIC component. Register
inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/dqs_zen_0_1
set/reset disagrees with another register in the OLOGIC component.
WARNING:Pack:2549 - The register "inst_ps2_wb_0/inst_ps2_core/ps2_clk_tx" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal "N25" does not match the ILOGIC SR signal
"inst_ps2_phy_0/Inst_debounce_clk/output_and0000".
The OLOGIC REV signal "inst_ps2_wb_0/inst_ps2_core/read_cs_FSM_FFd3" does not
match the ILOGIC REV signal
"inst_ps2_phy_0/Inst_debounce_clk/output_and0001".
WARNING:Pack:2549 - The register "inst_ps2_wb_0/inst_ps2_core/ps2_clk_tx_1" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal "N25" does not match the ILOGIC SR signal
"inst_ps2_phy_0/Inst_debounce_clk/output_and0000".
The OLOGIC REV signal "inst_ps2_wb_0/inst_ps2_core/read_cs_FSM_FFd3" does not
match the ILOGIC REV signal
"inst_ps2_phy_0/Inst_debounce_clk/output_and0001".
WARNING:Pack:2549 - The register "inst_ps2_wb_1/inst_ps2_core/ps2_clk_tx" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal "N21" does not match the ILOGIC SR signal
"inst_ps2_phy_1/Inst_debounce_clk/output_and0000".
The OLOGIC REV signal "inst_ps2_wb_1/inst_ps2_core/read_cs_FSM_FFd3" does not
match the ILOGIC REV signal
"inst_ps2_phy_1/Inst_debounce_clk/output_and0001".
WARNING:Pack:2549 - The register "inst_ps2_wb_1/inst_ps2_core/ps2_clk_tx_1" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal "N21" does not match the ILOGIC SR signal
"inst_ps2_phy_1/Inst_debounce_clk/output_and0000".
The OLOGIC REV signal "inst_ps2_wb_1/inst_ps2_core/read_cs_FSM_FFd3" does not
match the ILOGIC REV signal
"inst_ps2_phy_1/Inst_debounce_clk/output_and0001".
WARNING:Pack:2548 - The register "inst_gpio_wb/gpi1_reg_7" has the property
IOB=TRUE, but was not packed into the ILOGIC component. The ILOGIC component
already contains an IFF1.
WARNING:Pack:266 - The function generator
inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000026 failed to
merge with F5 multiplexer
inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000026_f6/MUXF5.I1
. Tried to combine two collections of symbols from different layers. The
alignment requirements of the two layers conflict. The design will exhibit
suboptimal timing.
WARNING:Pack:266 - The function generator
inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000028 failed to
merge with F5 multiplexer
inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000011_f6/MUXF5.I0
. Tried to combine two collections of symbols from different layers. The
alignment requirements of the two layers conflict. The design will exhibit
suboptimal timing.
WARNING:Pack:266 - The function generator
inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom0000231 failed to
merge with F5 multiplexer
inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000016_f6/MUXF5.I1
. Tried to combine two collections of symbols from different layers. The
alignment requirements of the two layers conflict. The design will exhibit
suboptimal timing.
WARNING:Pack:266 - The function generator
inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000024 failed to
merge with F5 multiplexer
inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000024_f6/MUXF5.I1
. Tried to combine two collections of symbols from different layers. The
alignment requirements of the two layers conflict. The design will exhibit
suboptimal timing.
WARNING:Pack:266 - The function generator
inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000032 failed to
merge with F5 multiplexer
inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom00007_f6/MUXF5.I0.
Tried to combine two collections of symbols from different layers. The
alignment requirements of the two layers conflict. The design will exhibit
suboptimal timing.
WARNING:Pack:266 - The function generator
inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000030 failed to
merge with F5 multiplexer
inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000030_f6/MUXF5.I1
. Tried to combine two collections of symbols from different layers. The
alignment requirements of the two layers conflict. The design will exhibit
suboptimal timing.
WARNING:Pack:266 - The function generator
inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom0000351 failed to
merge with F5 multiplexer
inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000035_f6/MUXF5.I0
. Tried to combine two collections of symbols from different layers. The
alignment requirements of the two layers conflict. The design will exhibit
suboptimal timing.
WARNING:Pack:266 - The function generator
inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000034 failed to
merge with F5 multiplexer
inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom00005_f6/MUXF5.I0.
Tried to combine two collections of symbols from different layers. The
alignment requirements of the two layers conflict. The design will exhibit
suboptimal timing.
WARNING:Pack:266 - The function generator
inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom0000271 failed to
merge with F5 multiplexer
inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000012_f6/MUXF5.I1
. Tried to combine two collections of symbols from different layers. The
alignment requirements of the two layers conflict. The design will exhibit
suboptimal timing.
WARNING:Pack:266 - The function generator
inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom0000251 failed to
merge with F5 multiplexer
inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000025_f6/MUXF5.I0
. Tried to combine two collections of symbols from different layers. The
alignment requirements of the two layers conflict. The design will exhibit
suboptimal timing.
WARNING:Pack:266 - The function generator
inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom0000331 failed to
merge with F5 multiplexer
inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000033_f6/MUXF5.I0
. Tried to combine two collections of symbols from different layers. The
alignment requirements of the two layers conflict. The design will exhibit
suboptimal timing.
WARNING:Pack:266 - The function generator
inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000036 failed to
merge with F5 multiplexer
inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom00003_f6/MUXF5.I0.
Tried to combine two collections of symbols from different layers. The
alignment requirements of the two layers conflict. The design will exhibit
suboptimal timing.
WARNING:Pack:266 - The function generator
inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom0000312 failed to
merge with F5 multiplexer
inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom00008_f6/MUXF5.I1.
Tried to combine two collections of symbols from different layers. The
alignment requirements of the two layers conflict. The design will exhibit
suboptimal timing.
WARNING:Pack:266 - The function generator
inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom0000291 failed to
merge with F5 multiplexer
inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000010_f6/MUXF5.I1
. Tried to combine two collections of symbols from different layers. The
alignment requirements of the two layers conflict. The design will exhibit
suboptimal timing.
WARNING:Place:838 - An IO Bus with more than one IO standard is found.
Components associated with this bus are as follows:
Comp: sys_vga_blue<0> IOSTANDARD = LVCMOS33
Comp: sys_vga_blue<1> IOSTANDARD = LVCMOS33
Comp: sys_vga_blue<2> IOSTANDARD = LVCMOS33
Comp: sys_vga_blue<3> IOSTANDARD = LVCMOS25
Comp: sys_vga_blue<4> IOSTANDARD = LVCMOS25
Comp: sys_vga_blue<5> IOSTANDARD = LVCMOS25
Comp: sys_vga_blue<6> IOSTANDARD = LVCMOS25
Comp: sys_vga_blue<7> IOSTANDARD = LVCMOS25
WARNING:Place:838 - An IO Bus with more than one IO standard is found.
Components associated with this bus are as follows:
Comp: sys_vga_green<0> IOSTANDARD = LVCMOS33
Comp: sys_vga_green<1> IOSTANDARD = LVCMOS33
Comp: sys_vga_green<2> IOSTANDARD = LVCMOS33
Comp: sys_vga_green<3> IOSTANDARD = LVCMOS25
Comp: sys_vga_green<4> IOSTANDARD = LVCMOS25
Comp: sys_vga_green<5> IOSTANDARD = LVCMOS25
Comp: sys_vga_green<6> IOSTANDARD = LVCMOS25
Comp: sys_vga_green<7> IOSTANDARD = LVCMOS25
WARNING:Place:838 - An IO Bus with more than one IO standard is found.
Components associated with this bus are as follows:
Comp: sys_vga_red<0> IOSTANDARD = LVCMOS33
Comp: sys_vga_red<1> IOSTANDARD = LVCMOS33
Comp: sys_vga_red<2> IOSTANDARD = LVCMOS33
Comp: sys_vga_red<3> IOSTANDARD = LVCMOS25
Comp: sys_vga_red<4> IOSTANDARD = LVCMOS25
Comp: sys_vga_red<5> IOSTANDARD = LVCMOS25
Comp: sys_vga_red<6> IOSTANDARD = LVCMOS25
Comp: sys_vga_red<7> IOSTANDARD = LVCMOS25
WARNING:PhysDesignRules:1236 - Unknown DCM_ADV feedback loop. The signal sys_sdr_clk_fb_IBUFG on the CLKFB pin of
DCM_ADV comp inst_clockgen/inst_DCM_SDRCLK_0 was driven by an IOB site but the signal loop could not be traced back
to the CLK0 pin of comp inst_clockgen/inst_DCM_SDRCLK_0. The signal out the CLK0 pin must drive an IOB input pin with
programming out to the PAD.
Section 3 - Informational
-------------------------
INFO:MapLib:564 - The following environment variables are currently set:
INFO:MapLib:591 - XIL_MAP_LOCWARN Value: 1
INFO:MapLib:159 - Net Timing constraints on signal sys_ac97_bit_clk are pushed
forward through input buffer.
INFO:MapLib:797 - Your design is targeting LX/SX Production Step 0/1/ES devices.
Please note that there are new specifications for the DCMs to guarantee
maximum frequency performance. If the DCM input clock might stop or if the
DCM reset might be asserted for an extended time, then use of the dcm_standby
macro may be required. Please see Answer Record 21127.
INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
0.000 to 85.000 Celsius)
INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to
1.260 Volts)
INFO:Pack:1650 - Map created a placed design.
INFO:PhysDesignRules:1437 - To achieve optimal frequency synthesis performance with the CLKFX and CLKFX180 outputs of
the DCM_ADV comp inst_clockgen/inst_DCM_VGA_FX, consult the device Data Sheet.
INFO:PhysDesignRules:1437 - To achieve optimal frequency synthesis performance with the CLKFX and CLKFX180 outputs of
the DCM_ADV comp inst_clockgen/inst_DCM_SYS_FX, consult the device Data Sheet.
Section 4 - Removed Logic Summary
---------------------------------
168 block(s) removed
4 block(s) optimized away
168 signal(s) removed
Section 5 - Removed Logic
-------------------------
The trimmed logic report below shows the logic removed from your design due to
sourceless or loadless signals, and VCC or ground connections. If the removal
of a signal or symbol results in the subsequent removal of an additional signal
or symbol, the message explaining that second removal will be indented. This
indentation will be repeated as a chain of related logic is removed.
To quickly locate the original cause for the removal of a chain of logic, look
above the place where that logic is listed in the trimming report, then locate
the lines that are least indented (begin at the leftmost edge).
The signal "sys_usb_d_15_IOBUF/N2" is sourceless and has been removed.
The signal "sys_usb_d_15_IOBUF/N3" is sourceless and has been removed.
The signal "sys_usb_d_14_IOBUF/N2" is sourceless and has been removed.
The signal "sys_usb_d_14_IOBUF/N3" is sourceless and has been removed.
The signal "sys_usb_d_13_IOBUF/N2" is sourceless and has been removed.
The signal "sys_usb_d_13_IOBUF/N3" is sourceless and has been removed.
The signal "sys_usb_d_12_IOBUF/N2" is sourceless and has been removed.
The signal "sys_usb_d_12_IOBUF/N3" is sourceless and has been removed.
The signal "sys_usb_d_11_IOBUF/N2" is sourceless and has been removed.
The signal "sys_usb_d_11_IOBUF/N3" is sourceless and has been removed.
The signal "sys_usb_d_10_IOBUF/N2" is sourceless and has been removed.
The signal "sys_usb_d_10_IOBUF/N3" is sourceless and has been removed.
The signal "sys_usb_d_9_IOBUF/N2" is sourceless and has been removed.
The signal "sys_usb_d_9_IOBUF/N3" is sourceless and has been removed.
The signal "sys_usb_d_8_IOBUF/N2" is sourceless and has been removed.
The signal "sys_usb_d_8_IOBUF/N3" is sourceless and has been removed.
The signal "sys_usb_d_7_IOBUF/N2" is sourceless and has been removed.
The signal "sys_usb_d_7_IOBUF/N3" is sourceless and has been removed.
The signal "sys_usb_d_6_IOBUF/N2" is sourceless and has been removed.
The signal "sys_usb_d_6_IOBUF/N3" is sourceless and has been removed.
The signal "sys_usb_d_5_IOBUF/N2" is sourceless and has been removed.
The signal "sys_usb_d_5_IOBUF/N3" is sourceless and has been removed.
The signal "sys_usb_d_4_IOBUF/N2" is sourceless and has been removed.
The signal "sys_usb_d_4_IOBUF/N3" is sourceless and has been removed.
The signal "sys_usb_d_3_IOBUF/N2" is sourceless and has been removed.
The signal "sys_usb_d_3_IOBUF/N3" is sourceless and has been removed.
The signal "sys_usb_d_2_IOBUF/N2" is sourceless and has been removed.
The signal "sys_usb_d_2_IOBUF/N3" is sourceless and has been removed.
The signal "sys_usb_d_1_IOBUF/N2" is sourceless and has been removed.
The signal "sys_usb_d_1_IOBUF/N3" is sourceless and has been removed.
The signal "sys_usb_d_0_IOBUF/N2" is sourceless and has been removed.
The signal "sys_usb_d_0_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_31_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_31_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_30_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_30_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_29_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_29_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_28_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_28_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_27_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_27_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_26_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_26_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_25_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_25_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_24_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_24_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_23_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_23_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_22_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_22_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_21_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_21_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_20_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_20_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_19_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_19_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_18_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_18_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_17_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_17_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_16_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_16_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_15_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_15_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_14_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_14_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_13_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_13_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_12_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_12_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_11_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_11_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_10_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_10_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_9_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_9_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_8_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_8_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_7_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_7_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_6_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_6_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_5_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_5_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_4_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_4_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_3_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_3_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_2_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_2_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_1_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_1_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_0_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_0_IOBUF/N3" is sourceless and has been removed.
The signal "inst_ps2_phy_1/IOBUF_inst_ps2_data/N2" is sourceless and has been
removed.
The signal "inst_ps2_phy_1/IOBUF_inst_ps2_data/N3" is sourceless and has been
removed.
The signal "inst_ps2_phy_1/IOBUF_inst_ps2_clk/N2" is sourceless and has been
removed.
The signal "inst_ps2_phy_1/IOBUF_inst_ps2_clk/N3" is sourceless and has been
removed.
The signal "inst_ps2_phy_0/IOBUF_inst_ps2_data/N2" is sourceless and has been
removed.
The signal "inst_ps2_phy_0/IOBUF_inst_ps2_data/N3" is sourceless and has been
removed.
The signal "inst_ps2_phy_0/IOBUF_inst_ps2_clk/N2" is sourceless and has been
removed.
The signal "inst_ps2_phy_0/IOBUF_inst_ps2_clk/N3" is sourceless and has been
removed.
The signal "sys_sdr_data_31_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_31_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_30_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_30_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_29_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_29_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_28_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_28_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_27_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_27_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_26_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_26_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_25_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_25_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_24_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_24_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_23_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_23_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_22_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_22_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_21_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_21_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_20_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_20_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_19_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_19_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_18_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_18_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_17_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_17_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_16_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_16_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_15_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_15_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_14_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_14_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_13_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_13_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_12_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_12_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_11_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_11_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_10_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_10_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_9_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_9_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_8_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_8_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_7_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_7_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_6_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_6_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_5_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_5_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_4_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_4_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_3_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_3_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_2_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_2_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_1_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_1_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_0_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_0_IOBUF/N3" is sourceless and has been removed.
Unused block "inst_ps2_phy_0/IOBUF_inst_ps2_clk/XST_GND" (ZERO) removed.
Unused block "inst_ps2_phy_0/IOBUF_inst_ps2_clk/XST_VCC" (ONE) removed.
Unused block "inst_ps2_phy_0/IOBUF_inst_ps2_data/XST_GND" (ZERO) removed.
Unused block "inst_ps2_phy_0/IOBUF_inst_ps2_data/XST_VCC" (ONE) removed.
Unused block "inst_ps2_phy_1/IOBUF_inst_ps2_clk/XST_GND" (ZERO) removed.
Unused block "inst_ps2_phy_1/IOBUF_inst_ps2_clk/XST_VCC" (ONE) removed.
Unused block "inst_ps2_phy_1/IOBUF_inst_ps2_data/XST_GND" (ZERO) removed.
Unused block "inst_ps2_phy_1/IOBUF_inst_ps2_data/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_0_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_0_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_10_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_10_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_11_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_11_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_12_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_12_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_13_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_13_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_14_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_14_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_15_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_15_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_16_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_16_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_17_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_17_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_18_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_18_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_19_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_19_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_1_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_1_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_20_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_20_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_21_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_21_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_22_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_22_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_23_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_23_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_24_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_24_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_25_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_25_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_26_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_26_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_27_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_27_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_28_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_28_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_29_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_29_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_2_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_2_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_30_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_30_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_31_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_31_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_3_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_3_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_4_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_4_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_5_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_5_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_6_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_6_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_7_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_7_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_8_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_8_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_9_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_9_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_0_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_0_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_10_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_10_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_11_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_11_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_12_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_12_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_13_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_13_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_14_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_14_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_15_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_15_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_16_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_16_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_17_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_17_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_18_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_18_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_19_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_19_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_1_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_1_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_20_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_20_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_21_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_21_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_22_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_22_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_23_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_23_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_24_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_24_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_25_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_25_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_26_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_26_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_27_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_27_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_28_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_28_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_29_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_29_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_2_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_2_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_30_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_30_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_31_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_31_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_3_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_3_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_4_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_4_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_5_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_5_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_6_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_6_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_7_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_7_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_8_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_8_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_9_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_9_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_usb_d_0_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_usb_d_0_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_usb_d_10_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_usb_d_10_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_usb_d_11_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_usb_d_11_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_usb_d_12_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_usb_d_12_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_usb_d_13_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_usb_d_13_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_usb_d_14_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_usb_d_14_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_usb_d_15_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_usb_d_15_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_usb_d_1_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_usb_d_1_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_usb_d_2_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_usb_d_2_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_usb_d_3_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_usb_d_3_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_usb_d_4_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_usb_d_4_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_usb_d_5_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_usb_d_5_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_usb_d_6_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_usb_d_6_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_usb_d_7_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_usb_d_7_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_usb_d_8_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_usb_d_8_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_usb_d_9_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_usb_d_9_IOBUF/XST_VCC" (ONE) removed.
Optimized Block(s):
TYPE BLOCK
GND XST_GND
VCC XST_VCC
GND inst_mips_top/XST_GND
VCC inst_mips_top/XST_VCC
To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.
Section 6 - IOB Properties
--------------------------
+-------------------------------------------------------------------------------------------------------------------------------------------------+
| IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB |
| | | | | Strength | Rate | | | Delay |
+-------------------------------------------------------------------------------------------------------------------------------------------------+
| sys_ac97_bit_clk | IOB | INPUT | LVCMOS33 | | | | | |
| sys_ac97_sdata_in | IOB | INPUT | LVCMOS33 | | | IFF1 | | |
| sys_ac97_sdata_out | IOB | OUTPUT | LVCMOS25 | 12 | FAST | OFF1 | | |
| sys_ac97_ssync | IOB | OUTPUT | LVCMOS25 | 12 | FAST | OFF1 | | |
| sys_btn<0> | IOB | INPUT | LVCMOS25 | | | IFF1 | PULLDOWN | |
| sys_btn<1> | IOB | INPUT | LVCMOS25 | | | IFF1 | PULLDOWN | |
| sys_btn<2> | IOB | INPUT | LVCMOS25 | | | IFF1 | PULLDOWN | |
| sys_btn<3> | IOB | INPUT | LVCMOS25 | | | IFF1 | PULLDOWN | |
| sys_btn<4> | IOB | INPUT | LVCMOS25 | | | IFF1 | PULLDOWN | |
| sys_clk_in | IOB | INPUT | LVCMOS33 | | | | | |
| sys_dip<0> | IOB | INPUT | LVCMOS33 | | | IFF1 | PULLDOWN | |
| sys_dip<1> | IOB | INPUT | LVCMOS33 | | | IFF1 | PULLDOWN | |
| sys_dip<2> | IOB | INPUT | LVCMOS33 | | | IFF1 | PULLDOWN | |
| sys_dip<3> | IOB | INPUT | LVCMOS33 | | | IFF1 | PULLDOWN | |
| sys_dip<4> | IOB | INPUT | LVCMOS33 | | | IFF1 | PULLDOWN | |
| sys_dip<5> | IOB | INPUT | LVCMOS33 | | | IFF1 | PULLDOWN | |
| sys_dip<6> | IOB | INPUT | LVCMOS33 | | | IFF1 | PULLDOWN | |
| sys_dip<7> | IOB | INPUT | LVCMOS33 | | | IFF1 | PULLDOWN | |
| sys_error<0> | IOB | OUTPUT | LVCMOS33 | 2 | SLOW | OFF1 | | |
| sys_error<1> | IOB | OUTPUT | LVCMOS33 | 2 | SLOW | OFF1 | | |
| sys_flash_a<0> | IOB | OUTPUT | LVDCI_33 | | | | | |
| sys_flash_a<1> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | |
| sys_flash_a<2> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | |
| sys_flash_a<3> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | |
| sys_flash_a<4> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | |
| sys_flash_a<5> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | |
| sys_flash_a<6> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | |
| sys_flash_a<7> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | |
| sys_flash_a<8> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | |
| sys_flash_a<9> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | |
| sys_flash_a<10> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | |
| sys_flash_a<11> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | |
| sys_flash_a<12> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | |
| sys_flash_a<13> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | |
| sys_flash_a<14> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | |
| sys_flash_a<15> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | |
| sys_flash_a<16> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | |
| sys_flash_a<17> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | |
| sys_flash_a<18> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | |
| sys_flash_a<19> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | |
| sys_flash_a<20> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | |
| sys_flash_a<21> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | |
| sys_flash_a<22> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | |
| sys_flash_a<23> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | |
| sys_flash_a<24> | IOB | OUTPUT | LVDCI_33 | | | | | |
| sys_flash_ac97_rstn | IOB | OUTPUT | LVCMOS33 | 8 | FAST | | | |
| sys_flash_byten | IOB | OUTPUT | LVCMOS33 | 8 | FAST | | | |
| sys_flash_ce | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | |
| sys_flash_d<0> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | |
| | | | | | | OFF1 | | |
| | | | | | | TFF1 | | |
| sys_flash_d<1> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | |
| | | | | | | OFF1 | | |
| | | | | | | TFF1 | | |
| sys_flash_d<2> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | |
| | | | | | | OFF1 | | |
| | | | | | | TFF1 | | |
| sys_flash_d<3> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | |
| | | | | | | OFF1 | | |
| | | | | | | TFF1 | | |
| sys_flash_d<4> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | |
| | | | | | | OFF1 | | |
| | | | | | | TFF1 | | |
| sys_flash_d<5> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | |
| | | | | | | OFF1 | | |
| | | | | | | TFF1 | | |
| sys_flash_d<6> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | |
| | | | | | | OFF1 | | |
| | | | | | | TFF1 | | |
| sys_flash_d<7> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | |
| | | | | | | OFF1 | | |
| | | | | | | TFF1 | | |
| sys_flash_d<8> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | |
| | | | | | | OFF1 | | |
| | | | | | | TFF1 | | |
| sys_flash_d<9> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | |
| | | | | | | OFF1 | | |
| | | | | | | TFF1 | | |
| sys_flash_d<10> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | |
| | | | | | | OFF1 | | |
| | | | | | | TFF1 | | |
| sys_flash_d<11> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | |
| | | | | | | OFF1 | | |
| | | | | | | TFF1 | | |
| sys_flash_d<12> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | |
| | | | | | | OFF1 | | |
| | | | | | | TFF1 | | |
| sys_flash_d<13> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | |
| | | | | | | OFF1 | | |
| | | | | | | TFF1 | | |
| sys_flash_d<14> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | |
| | | | | | | OFF1 | | |
| | | | | | | TFF1 | | |
| sys_flash_d<15> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | |
| | | | | | | OFF1 | | |
| | | | | | | TFF1 | | |
| sys_flash_d<16> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | |
| | | | | | | OFF1 | | |
| | | | | | | TFF1 | | |
| sys_flash_d<17> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | |
| | | | | | | OFF1 | | |
| | | | | | | TFF1 | | |
| sys_flash_d<18> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | |
| | | | | | | OFF1 | | |
| | | | | | | TFF1 | | |
| sys_flash_d<19> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | |
| | | | | | | OFF1 | | |
| | | | | | | TFF1 | | |
| sys_flash_d<20> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | |
| | | | | | | OFF1 | | |
| | | | | | | TFF1 | | |
| sys_flash_d<21> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | |
| | | | | | | OFF1 | | |
| | | | | | | TFF1 | | |
| sys_flash_d<22> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | |
| | | | | | | OFF1 | | |
| | | | | | | TFF1 | | |
| sys_flash_d<23> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | |
| | | | | | | OFF1 | | |
| | | | | | | TFF1 | | |
| sys_flash_d<24> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | |
| | | | | | | OFF1 | | |
| | | | | | | TFF1 | | |
| sys_flash_d<25> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | |
| | | | | | | OFF1 | | |
| | | | | | | TFF1 | | |
| sys_flash_d<26> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | |
| | | | | | | OFF1 | | |
| | | | | | | TFF1 | | |
| sys_flash_d<27> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | |
| | | | | | | OFF1 | | |
| | | | | | | TFF1 | | |
| sys_flash_d<28> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | |
| | | | | | | OFF1 | | |
| | | | | | | TFF1 | | |
| sys_flash_d<29> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | |
| | | | | | | OFF1 | | |
| | | | | | | TFF1 | | |
| sys_flash_d<30> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | |
| | | | | | | OFF1 | | |
| | | | | | | TFF1 | | |
| sys_flash_d<31> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | |
| | | | | | | OFF1 | | |
| | | | | | | TFF1 | | |
| sys_flash_rdn | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | |
| sys_flash_wrn | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | |
| sys_lcd_d<0> | IOB | OUTPUT | LVCMOS33 | 2 | SLOW | | PULLDOWN | |
| sys_lcd_d<1> | IOB | OUTPUT | LVCMOS33 | 2 | SLOW | | PULLDOWN | |
| sys_lcd_d<2> | IOB | OUTPUT | LVCMOS33 | 2 | SLOW | | PULLDOWN | |
| sys_lcd_d<3> | IOB | OUTPUT | LVCMOS33 | 2 | SLOW | | PULLDOWN | |
| sys_lcd_e | IOB | OUTPUT | LVCMOS33 | 2 | SLOW | | | |
| sys_lcd_rs | IOB | OUTPUT | LVCMOS33 | 2 | SLOW | | | |
| sys_lcd_rw | IOB | OUTPUT | LVCMOS33 | 2 | SLOW | | | |
| sys_led<0> | IOB | OUTPUT | LVCMOS25 | 2 | SLOW | OFF1 | | |
| sys_led<1> | IOB | OUTPUT | LVCMOS25 | 2 | SLOW | OFF1 | | |
| sys_led<2> | IOB | OUTPUT | LVCMOS25 | 2 | SLOW | OFF1 | | |
| sys_led<3> | IOB | OUTPUT | LVCMOS25 | 2 | SLOW | OFF1 | | |
| sys_led<4> | IOB | OUTPUT | LVCMOS25 | 2 | SLOW | OFF1 | | |
| sys_led<5> | IOB | OUTPUT | LVCMOS25 | 2 | SLOW | OFF1 | | |
| sys_led<6> | IOB | OUTPUT | LVCMOS25 | 2 | SLOW | OFF1 | | |
| sys_led<7> | IOB | OUTPUT | LVCMOS25 | 2 | SLOW | OFF1 | | |
| sys_led<8> | IOB | OUTPUT | LVCMOS25 | 2 | SLOW | OFF1 | | |
| sys_ps2_0_clk | IOB | BIDIR | LVCMOS25 | 2 | SLOW | IFF1 | | |
| sys_ps2_0_data | IOB | BIDIR | LVCMOS25 | 2 | SLOW | IFF1 | | |
| sys_ps2_1_clk | IOB | BIDIR | LVCMOS25 | 2 | SLOW | IFF1 | | |
| sys_ps2_1_data | IOB | BIDIR | LVCMOS25 | 2 | SLOW | IFF1 | | |
| sys_rst_n_in | IOB | INPUT | LVCMOS25 | | | | PULLUP | |
| sys_sdr_a_q<0> | IOB | OUTPUT | SSTL2_I | | | OFF1 | | |
| sys_sdr_a_q<1> | IOB | OUTPUT | SSTL2_I | | | OFF1 | | |
| sys_sdr_a_q<2> | IOB | OUTPUT | SSTL2_I | | | OFF1 | | |
| sys_sdr_a_q<3> | IOB | OUTPUT | SSTL2_I | | | OFF1 | | |
| sys_sdr_a_q<4> | IOB | OUTPUT | SSTL2_I | | | OFF1 | | |
| sys_sdr_a_q<5> | IOB | OUTPUT | SSTL2_I | | | OFF1 | | |
| sys_sdr_a_q<6> | IOB | OUTPUT | SSTL2_I | | | OFF1 | | |
| sys_sdr_a_q<7> | IOB | OUTPUT | SSTL2_I | | | OFF1 | | |
| sys_sdr_a_q<8> | IOB | OUTPUT | SSTL2_I | | | OFF1 | | |
| sys_sdr_a_q<9> | IOB | OUTPUT | SSTL2_I | | | OFF1 | | |
| sys_sdr_a_q<10> | IOB | OUTPUT | SSTL2_I | | | OFF1 | | |
| sys_sdr_a_q<11> | IOB | OUTPUT | SSTL2_I | | | OFF1 | | |
| sys_sdr_a_q<12> | IOB | OUTPUT | SSTL2_I | | | OFF1 | | |
| sys_sdr_ba_q<0> | IOB | OUTPUT | SSTL2_I | | | OFF1 | | |
| sys_sdr_ba_q<1> | IOB | OUTPUT | SSTL2_I | | | OFF1 | | |
| sys_sdr_cas_qn | IOB | OUTPUT | SSTL2_I | | | OFF1 | | |
| sys_sdr_cke_q | IOB | OUTPUT | SSTL2_I | | | OFF1 | | |
| sys_sdr_clk_fb | IOB | INPUT | LVCMOS25 | | | | | |
| sys_sdr_clk_n | IOB | OUTPUT | SSTL2_I | | | OFF1 | | |
| | ODDR:OPPOSITE | | | | | OFF2 | | |
| | | | | | | OFFDDRA | | |
| sys_sdr_clk_p | IOB | OUTPUT | SSTL2_I | | | OFF1 | | |
| | ODDR:OPPOSITE | | | | | OFF2 | | |
| | | | | | | OFFDDRA | | |
| sys_sdr_cs_qn | IOB | OUTPUT | SSTL2_I | | | OFF1 | | |
| sys_sdr_data<0> | IOB | BIDIR | SSTL2_II | | | IFF1 | | |
| | IDDR:SAMEODDR:SA | | | | | IFF2 | | |
| | | | | | | IFF4 | | |
| | | | | | | OFF1 | | |
| | | | | | | OFF2 | | |
| | | | | | | OFF3 | | |
| | | | | | | OFFDDRB | | |
| sys_sdr_data<1> | IOB | BIDIR | SSTL2_II | | | IFF1 | | |
| | IDDR:SAMEODDR:SA | | | | | IFF2 | | |
| | | | | | | IFF4 | | |
| | | | | | | OFF1 | | |
| | | | | | | OFF2 | | |
| | | | | | | OFF3 | | |
| | | | | | | OFFDDRB | | |
| sys_sdr_data<2> | IOB | BIDIR | SSTL2_II | | | IFF1 | | |
| | IDDR:SAMEODDR:SA | | | | | IFF2 | | |
| | | | | | | IFF4 | | |
| | | | | | | OFF1 | | |
| | | | | | | OFF2 | | |
| | | | | | | OFF3 | | |
| | | | | | | OFFDDRB | | |
| sys_sdr_data<3> | IOB | BIDIR | SSTL2_II | | | IFF1 | | |
| | IDDR:SAMEODDR:SA | | | | | IFF2 | | |
| | | | | | | IFF4 | | |
| | | | | | | OFF1 | | |
| | | | | | | OFF2 | | |
| | | | | | | OFF3 | | |
| | | | | | | OFFDDRB | | |
| sys_sdr_data<4> | IOB | BIDIR | SSTL2_II | | | IFF1 | | |
| | IDDR:SAMEODDR:SA | | | | | IFF2 | | |
| | | | | | | IFF4 | | |
| | | | | | | OFF1 | | |
| | | | | | | OFF2 | | |
| | | | | | | OFF3 | | |
| | | | | | | OFFDDRB | | |
| sys_sdr_data<5> | IOB | BIDIR | SSTL2_II | | | IFF1 | | |
| | IDDR:SAMEODDR:SA | | | | | IFF2 | | |
| | | | | | | IFF4 | | |
| | | | | | | OFF1 | | |
| | | | | | | OFF2 | | |
| | | | | | | OFF3 | | |
| | | | | | | OFFDDRB | | |
| sys_sdr_data<6> | IOB | BIDIR | SSTL2_II | | | IFF1 | | |
| | IDDR:SAMEODDR:SA | | | | | IFF2 | | |
| | | | | | | IFF4 | | |
| | | | | | | OFF1 | | |
| | | | | | | OFF2 | | |
| | | | | | | OFF3 | | |
| | | | | | | OFFDDRB | | |
| sys_sdr_data<7> | IOB | BIDIR | SSTL2_II | | | IFF1 | | |
| | IDDR:SAMEODDR:SA | | | | | IFF2 | | |
| | | | | | | IFF4 | | |
| | | | | | | OFF1 | | |
| | | | | | | OFF2 | | |
| | | | | | | OFF3 | | |
| | | | | | | OFFDDRB | | |
| sys_sdr_data<8> | IOB | BIDIR | SSTL2_II | | | IFF1 | | |
| | IDDR:SAMEODDR:SA | | | | | IFF2 | | |
| | | | | | | IFF4 | | |
| | | | | | | OFF1 | | |
| | | | | | | OFF2 | | |
| | | | | | | OFF3 | | |
| | | | | | | OFFDDRB | | |
| sys_sdr_data<9> | IOB | BIDIR | SSTL2_II | | | IFF1 | | |
| | IDDR:SAMEODDR:SA | | | | | IFF2 | | |
| | | | | | | IFF4 | | |
| | | | | | | OFF1 | | |
| | | | | | | OFF2 | | |
| | | | | | | OFF3 | | |
| | | | | | | OFFDDRB | | |
| sys_sdr_data<10> | IOB | BIDIR | SSTL2_II | | | IFF1 | | |
| | IDDR:SAMEODDR:SA | | | | | IFF2 | | |
| | | | | | | IFF4 | | |
| | | | | | | OFF1 | | |
| | | | | | | OFF2 | | |
| | | | | | | OFF3 | | |
| | | | | | | OFFDDRB | | |
| sys_sdr_data<11> | IOB | BIDIR | SSTL2_II | | | IFF1 | | |
| | IDDR:SAMEODDR:SA | | | | | IFF2 | | |
| | | | | | | IFF4 | | |
| | | | | | | OFF1 | | |
| | | | | | | OFF2 | | |
| | | | | | | OFF3 | | |
| | | | | | | OFFDDRB | | |
| sys_sdr_data<12> | IOB | BIDIR | SSTL2_II | | | IFF1 | | |
| | IDDR:SAMEODDR:SA | | | | | IFF2 | | |
| | | | | | | IFF4 | | |
| | | | | | | OFF1 | | |
| | | | | | | OFF2 | | |
| | | | | | | OFF3 | | |
| | | | | | | OFFDDRB | | |
| sys_sdr_data<13> | IOB | BIDIR | SSTL2_II | | | IFF1 | | |
| | IDDR:SAMEODDR:SA | | | | | IFF2 | | |
| | | | | | | IFF4 | | |
| | | | | | | OFF1 | | |
| | | | | | | OFF2 | | |
| | | | | | | OFF3 | | |
| | | | | | | OFFDDRB | | |
| sys_sdr_data<14> | IOB | BIDIR | SSTL2_II | | | IFF1 | | |
| | IDDR:SAMEODDR:SA | | | | | IFF2 | | |
| | | | | | | IFF4 | | |
| | | | | | | OFF1 | | |
| | | | | | | OFF2 | | |
| | | | | | | OFF3 | | |
| | | | | | | OFFDDRB | | |
| sys_sdr_data<15> | IOB | BIDIR | SSTL2_II | | | IFF1 | | |
| | IDDR:SAMEODDR:SA | | | | | IFF2 | | |
| | | | | | | IFF4 | | |
| | | | | | | OFF1 | | |
| | | | | | | OFF2 | | |
| | | | | | | OFF3 | | |
| | | | | | | OFFDDRB | | |
| sys_sdr_data<16> | IOB | BIDIR | SSTL2_II | | | IFF1 | | |
| | IDDR:SAMEODDR:SA | | | | | IFF2 | | |
| | | | | | | IFF4 | | |
| | | | | | | OFF1 | | |
| | | | | | | OFF2 | | |
| | | | | | | OFF3 | | |
| | | | | | | OFFDDRB | | |
| sys_sdr_data<17> | IOB | BIDIR | SSTL2_II | | | IFF1 | | |
| | IDDR:SAMEODDR:SA | | | | | IFF2 | | |
| | | | | | | IFF4 | | |
| | | | | | | OFF1 | | |
| | | | | | | OFF2 | | |
| | | | | | | OFF3 | | |
| | | | | | | OFFDDRB | | |
| sys_sdr_data<18> | IOB | BIDIR | SSTL2_II | | | IFF1 | | |
| | IDDR:SAMEODDR:SA | | | | | IFF2 | | |
| | | | | | | IFF4 | | |
| | | | | | | OFF1 | | |
| | | | | | | OFF2 | | |
| | | | | | | OFF3 | | |
| | | | | | | OFFDDRB | | |
| sys_sdr_data<19> | IOB | BIDIR | SSTL2_II | | | IFF1 | | |
| | IDDR:SAMEODDR:SA | | | | | IFF2 | | |
| | | | | | | IFF4 | | |
| | | | | | | OFF1 | | |
| | | | | | | OFF2 | | |
| | | | | | | OFF3 | | |
| | | | | | | OFFDDRB | | |
| sys_sdr_data<20> | IOB | BIDIR | SSTL2_II | | | IFF1 | | |
| | IDDR:SAMEODDR:SA | | | | | IFF2 | | |
| | | | | | | IFF4 | | |
| | | | | | | OFF1 | | |
| | | | | | | OFF2 | | |
| | | | | | | OFF3 | | |
| | | | | | | OFFDDRB | | |
| sys_sdr_data<21> | IOB | BIDIR | SSTL2_II | | | IFF1 | | |
| | IDDR:SAMEODDR:SA | | | | | IFF2 | | |
| | | | | | | IFF4 | | |
| | | | | | | OFF1 | | |
| | | | | | | OFF2 | | |
| | | | | | | OFF3 | | |
| | | | | | | OFFDDRB | | |
| sys_sdr_data<22> | IOB | BIDIR | SSTL2_II | | | IFF1 | | |
| | IDDR:SAMEODDR:SA | | | | | IFF2 | | |
| | | | | | | IFF4 | | |
| | | | | | | OFF1 | | |
| | | | | | | OFF2 | | |
| | | | | | | OFF3 | | |
| | | | | | | OFFDDRB | | |
| sys_sdr_data<23> | IOB | BIDIR | SSTL2_II | | | IFF1 | | |
| | IDDR:SAMEODDR:SA | | | | | IFF2 | | |
| | | | | | | IFF4 | | |
| | | | | | | OFF1 | | |
| | | | | | | OFF2 | | |
| | | | | | | OFF3 | | |
| | | | | | | OFFDDRB | | |
| sys_sdr_data<24> | IOB | BIDIR | SSTL2_II | | | IFF1 | | |
| | IDDR:SAMEODDR:SA | | | | | IFF2 | | |
| | | | | | | IFF4 | | |
| | | | | | | OFF1 | | |
| | | | | | | OFF2 | | |
| | | | | | | OFF3 | | |
| | | | | | | OFFDDRB | | |
| sys_sdr_data<25> | IOB | BIDIR | SSTL2_II | | | IFF1 | | |
| | IDDR:SAMEODDR:SA | | | | | IFF2 | | |
| | | | | | | IFF4 | | |
| | | | | | | OFF1 | | |
| | | | | | | OFF2 | | |
| | | | | | | OFF3 | | |
| | | | | | | OFFDDRB | | |
| sys_sdr_data<26> | IOB | BIDIR | SSTL2_II | | | IFF1 | | |
| | IDDR:SAMEODDR:SA | | | | | IFF2 | | |
| | | | | | | IFF4 | | |
| | | | | | | OFF1 | | |
| | | | | | | OFF2 | | |
| | | | | | | OFF3 | | |
| | | | | | | OFFDDRB | | |
| sys_sdr_data<27> | IOB | BIDIR | SSTL2_II | | | IFF1 | | |
| | IDDR:SAMEODDR:SA | | | | | IFF2 | | |
| | | | | | | IFF4 | | |
| | | | | | | OFF1 | | |
| | | | | | | OFF2 | | |
| | | | | | | OFF3 | | |
| | | | | | | OFFDDRB | | |
| sys_sdr_data<28> | IOB | BIDIR | SSTL2_II | | | IFF1 | | |
| | IDDR:SAMEODDR:SA | | | | | IFF2 | | |
| | | | | | | IFF4 | | |
| | | | | | | OFF1 | | |
| | | | | | | OFF2 | | |
| | | | | | | OFF3 | | |
| | | | | | | OFFDDRB | | |
| sys_sdr_data<29> | IOB | BIDIR | SSTL2_II | | | IFF1 | | |
| | IDDR:SAMEODDR:SA | | | | | IFF2 | | |
| | | | | | | IFF4 | | |
| | | | | | | OFF1 | | |
| | | | | | | OFF2 | | |
| | | | | | | OFF3 | | |
| | | | | | | OFFDDRB | | |
| sys_sdr_data<30> | IOB | BIDIR | SSTL2_II | | | IFF1 | | |
| | IDDR:SAMEODDR:SA | | | | | IFF2 | | |
| | | | | | | IFF4 | | |
| | | | | | | OFF1 | | |
| | | | | | | OFF2 | | |
| | | | | | | OFF3 | | |
| | | | | | | OFFDDRB | | |
| sys_sdr_data<31> | IOB | BIDIR | SSTL2_II | | | IFF1 | | |
| | IDDR:SAMEODDR:SA | | | | | IFF2 | | |
| | | | | | | IFF4 | | |
| | | | | | | OFF1 | | |
| | | | | | | OFF2 | | |
| | | | | | | OFF3 | | |
| | | | | | | OFFDDRB | | |
| sys_sdr_dm_q<0> | IOB | OUTPUT | SSTL2_II | | | OFF1 | | |
| | ODDR:SAME | | | | | OFF2 | | |
| | | | | | | OFF3 | | |
| | | | | | | OFFDDRB | | |
| sys_sdr_dm_q<1> | IOB | OUTPUT | SSTL2_II | | | OFF1 | | |
| | ODDR:SAME | | | | | OFF2 | | |
| | | | | | | OFF3 | | |
| | | | | | | OFFDDRB | | |
| sys_sdr_dm_q<2> | IOB | OUTPUT | SSTL2_II | | | OFF1 | | |
| | ODDR:SAME | | | | | OFF2 | | |
| | | | | | | OFF3 | | |
| | | | | | | OFFDDRB | | |
| sys_sdr_dm_q<3> | IOB | OUTPUT | SSTL2_II | | | OFF1 | | |
| | ODDR:SAME | | | | | OFF2 | | |
| | | | | | | OFF3 | | |
| | | | | | | OFFDDRB | | |
| sys_sdr_dqs_q<0> | IOB | OUTPUT | SSTL2_II | | | OFF1 | | |
| | ODDR:OPPOSITE | | | | | OFF2 | | |
| | | | | | | OFFDDRA | | |
| sys_sdr_dqs_q<1> | IOB | OUTPUT | SSTL2_II | | | OFF1 | | |
| | ODDR:OPPOSITE | | | | | OFF2 | | |
| | | | | | | OFFDDRA | | |
| sys_sdr_dqs_q<2> | IOB | OUTPUT | SSTL2_II | | | OFF1 | | |
| | ODDR:OPPOSITE | | | | | OFF2 | | |
| | | | | | | OFFDDRA | | |
| sys_sdr_dqs_q<3> | IOB | OUTPUT | SSTL2_II | | | OFF1 | | |
| | ODDR:OPPOSITE | | | | | OFF2 | | |
| | | | | | | OFFDDRA | | |
| sys_sdr_ras_qn | IOB | OUTPUT | SSTL2_I | | | OFF1 | | |
| sys_sdr_we_qn | IOB | OUTPUT | SSTL2_I | | | OFF1 | | |
| sys_uart0_rx | IOB | INPUT | LVCMOS33 | | | IFF1 | | |
| sys_uart0_tx | IOB | OUTPUT | LVCMOS33 | 12 | SLOW | OFF1 | | |
| sys_uart1_rx | IOB | INPUT | LVCMOS33 | | | | | |
| sys_uart1_tx | IOB | OUTPUT | LVCMOS33 | 12 | SLOW | | | |
| sys_uart2_rx | IOB | INPUT | LVCMOS33 | | | | | |
| sys_uart2_tx | IOB | OUTPUT | LVCMOS33 | 12 | SLOW | | | |
| sys_uart3_rx | IOB | INPUT | LVCMOS33 | | | | | |
| sys_uart3_tx | IOB | OUTPUT | LVCMOS33 | 12 | SLOW | | | |
| sys_usb_a<0> | IOB | OUTPUT | LVCMOS33 | 12 | SLOW | OFF1 | | |
| sys_usb_a<1> | IOB | OUTPUT | LVCMOS33 | 12 | SLOW | OFF1 | | |
| sys_usb_csn | IOB | OUTPUT | LVCMOS33 | 8 | FAST | OFF1 | | |
| sys_usb_d<0> | IOB | BIDIR | LVCMOS33 | 8 | FAST | IFF1 | PULLDOWN | |
| | | | | | | OFF1 | | |
| | | | | | | TFF1 | | |
| sys_usb_d<1> | IOB | BIDIR | LVCMOS33 | 8 | FAST | IFF1 | PULLDOWN | |
| | | | | | | OFF1 | | |
| | | | | | | TFF1 | | |
| sys_usb_d<2> | IOB | BIDIR | LVCMOS33 | 8 | FAST | IFF1 | PULLDOWN | |
| | | | | | | OFF1 | | |
| | | | | | | TFF1 | | |
| sys_usb_d<3> | IOB | BIDIR | LVCMOS33 | 8 | FAST | IFF1 | PULLDOWN | |
| | | | | | | OFF1 | | |
| | | | | | | TFF1 | | |
| sys_usb_d<4> | IOB | BIDIR | LVCMOS33 | 8 | FAST | IFF1 | PULLDOWN | |
| | | | | | | OFF1 | | |
| | | | | | | TFF1 | | |
| sys_usb_d<5> | IOB | BIDIR | LVCMOS33 | 8 | FAST | IFF1 | PULLDOWN | |
| | | | | | | OFF1 | | |
| | | | | | | TFF1 | | |
| sys_usb_d<6> | IOB | BIDIR | LVCMOS33 | 8 | FAST | IFF1 | PULLDOWN | |
| | | | | | | OFF1 | | |
| | | | | | | TFF1 | | |
| sys_usb_d<7> | IOB | BIDIR | LVCMOS33 | 8 | FAST | IFF1 | PULLDOWN | |
| | | | | | | OFF1 | | |
| | | | | | | TFF1 | | |
| sys_usb_d<8> | IOB | BIDIR | LVCMOS33 | 8 | FAST | IFF1 | PULLDOWN | |
| | | | | | | OFF1 | | |
| | | | | | | TFF1 | | |
| sys_usb_d<9> | IOB | BIDIR | LVCMOS33 | 8 | FAST | IFF1 | PULLDOWN | |
| | | | | | | OFF1 | | |
| | | | | | | TFF1 | | |
| sys_usb_d<10> | IOB | BIDIR | LVCMOS33 | 8 | FAST | IFF1 | PULLDOWN | |
| | | | | | | OFF1 | | |
| | | | | | | TFF1 | | |
| sys_usb_d<11> | IOB | BIDIR | LVCMOS33 | 8 | FAST | IFF1 | PULLDOWN | |
| | | | | | | OFF1 | | |
| | | | | | | TFF1 | | |
| sys_usb_d<12> | IOB | BIDIR | LVCMOS33 | 8 | FAST | IFF1 | PULLDOWN | |
| | | | | | | OFF1 | | |
| | | | | | | TFF1 | | |
| sys_usb_d<13> | IOB | BIDIR | LVCMOS33 | 8 | FAST | IFF1 | PULLDOWN | |
| | | | | | | OFF1 | | |
| | | | | | | TFF1 | | |
| sys_usb_d<14> | IOB | BIDIR | LVCMOS33 | 8 | FAST | IFF1 | PULLDOWN | |
| | | | | | | OFF1 | | |
| | | | | | | TFF1 | | |
| sys_usb_d<15> | IOB | BIDIR | LVCMOS33 | 8 | FAST | IFF1 | PULLDOWN | |
| | | | | | | OFF1 | | |
| | | | | | | TFF1 | | |
| sys_usb_int | IOB | INPUT | LVCMOS33 | | | | PULLDOWN | |
| sys_usb_rdn | IOB | OUTPUT | LVCMOS33 | 8 | FAST | OFF1 | | |
| sys_usb_rstn | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
| sys_usb_wrn | IOB | OUTPUT | LVCMOS33 | 8 | FAST | OFF1 | | |
| sys_vga_blank_n | IOB | OUTPUT | LVCMOS33 | 8 | FAST | | | |
| sys_vga_blue<0> | IOB | OUTPUT | LVCMOS33 | 8 | FAST | OFF1 | | |
| sys_vga_blue<1> | IOB | OUTPUT | LVCMOS33 | 8 | FAST | OFF1 | | |
| sys_vga_blue<2> | IOB | OUTPUT | LVCMOS33 | 8 | FAST | OFF1 | | |
| sys_vga_blue<3> | IOB | OUTPUT | LVCMOS25 | 8 | FAST | OFF1 | | |
| sys_vga_blue<4> | IOB | OUTPUT | LVCMOS25 | 8 | FAST | OFF1 | | |
| sys_vga_blue<5> | IOB | OUTPUT | LVCMOS25 | 8 | FAST | OFF1 | | |
| sys_vga_blue<6> | IOB | OUTPUT | LVCMOS25 | 8 | FAST | OFF1 | | |
| sys_vga_blue<7> | IOB | OUTPUT | LVCMOS25 | 8 | FAST | OFF1 | | |
| sys_vga_clk | IOB | OUTPUT | LVDCI_33 | | | | | |
| sys_vga_green<0> | IOB | OUTPUT | LVCMOS33 | 8 | FAST | OFF1 | | |
| sys_vga_green<1> | IOB | OUTPUT | LVCMOS33 | 8 | FAST | OFF1 | | |
| sys_vga_green<2> | IOB | OUTPUT | LVCMOS33 | 8 | FAST | OFF1 | | |
| sys_vga_green<3> | IOB | OUTPUT | LVCMOS25 | 8 | FAST | OFF1 | | |
| sys_vga_green<4> | IOB | OUTPUT | LVCMOS25 | 8 | FAST | OFF1 | | |
| sys_vga_green<5> | IOB | OUTPUT | LVCMOS25 | 8 | FAST | OFF1 | | |
| sys_vga_green<6> | IOB | OUTPUT | LVCMOS25 | 8 | FAST | OFF1 | | |
| sys_vga_green<7> | IOB | OUTPUT | LVCMOS25 | 8 | FAST | OFF1 | | |
| sys_vga_hsync | IOB | OUTPUT | LVCMOS25 | 8 | FAST | OFF1 | | |
| sys_vga_red<0> | IOB | OUTPUT | LVCMOS33 | 8 | FAST | OFF1 | | |
| sys_vga_red<1> | IOB | OUTPUT | LVCMOS33 | 8 | FAST | OFF1 | | |
| sys_vga_red<2> | IOB | OUTPUT | LVCMOS33 | 8 | FAST | OFF1 | | |
| sys_vga_red<3> | IOB | OUTPUT | LVCMOS25 | 8 | FAST | OFF1 | | |
| sys_vga_red<4> | IOB | OUTPUT | LVCMOS25 | 8 | FAST | OFF1 | | |
| sys_vga_red<5> | IOB | OUTPUT | LVCMOS25 | 8 | FAST | OFF1 | | |
| sys_vga_red<6> | IOB | OUTPUT | LVCMOS25 | 8 | FAST | OFF1 | | |
| sys_vga_red<7> | IOB | OUTPUT | LVCMOS25 | 8 | FAST | OFF1 | | |
| sys_vga_sync_n | IOB | OUTPUT | LVCMOS33 | 8 | FAST | | | |
| sys_vga_vsync | IOB | OUTPUT | LVCMOS25 | 8 | FAST | OFF1 | | |
+-------------------------------------------------------------------------------------------------------------------------------------------------+
Section 7 - RPMs
----------------
Section 8 - Guide Report
------------------------
Guide not run on this design.
Section 9 - Area Group and Partition Summary
--------------------------------------------
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Area Group Information
----------------------
Area Group "AG_inst_mips_top"
No COMPRESSION specified for Area Group "AG_inst_mips_top"
RANGE: SLICE_X0Y53:SLICE_X39Y0
RANGE:
RAMB16_X0Y0:RAMB16_X0Y6,RAMB16_X1Y0:RAMB16_X1Y6,RAMB16_X2Y0:RAMB16_X2Y6,RAMB16_X
3Y0:RAMB16_X3Y6
Area Group Logic Utilization:
Number of Slice Flip Flops: 1,951 out of 4,320 45%
Logic Distribution:
Number of occupied Slices: 2,157 out of 2,160 99%
Number of Slices containing only related logic: 2,157 out of 2,157 100%
Total Number of 4 input LUTs: 4,308 out of 4,320 99%
Number used as logic: 3,648
Number used as route-thru: 49
Number used as 16x1 RAMs: 2
Number used as Dual Port RAMs: 586
(Two LUTs used per Dual Port RAM)
Number used as Shift registers: 23
Number of Block RAMs: 27 out of 28 96%
Section 10 - Modular Design Summary
-----------------------------------
Modular Design not used for this design.
Section 11 - Timing Report
--------------------------
A logic-level (pre-route) timing report can be generated by using Xilinx static
timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the
mapped NCD and PCF files. Please note that this timing report will be generated
using estimated delay information. For accurate numbers, please generate a
timing report with the post Place and Route NCD file.
For more information about the Timing Analyzer, consult the Xilinx Timing
Analyzer Reference Manual; for more information about TRCE, consult the Xilinx
Development System Reference Guide "TRACE" chapter.
Section 12 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings
Section 13 - Control Set Information
------------------------------------
No control set information for this architecture.
Section 14 - Utilization by Hierarchy
-------------------------------------
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| Module | Partition | Slices | Slice Reg | LUTs | LUTRAM | BRAM/FIFO | DSP48 | BUFG | BUFIO | BUFR | DCM | Full Hierarchical Name |
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| mips_sys/ | | 1395/8308 | 28/5411 | 849/9036 | 2/1000 | 0/51 | 0/0 | 2/12 | 0/0 | 0/0 | 0/4 | mips_sys |
| +inst_ac97_wb | | 183/796 | 118/672 | 186/631 | 0/0 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb |
| ++inst_ac_io | | 20/574 | 13/525 | 29/380 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io |
| +++inst_ac_in | | 261/265 | 258/262 | 98/103 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io/inst_ac_in |
| ++++singleshot_inst1 | | 2/2 | 2/2 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io/inst_ac_in/singleshot_inst1 |
| ++++singleshot_inst2 | | 2/2 | 2/2 | 3/3 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io/inst_ac_in/singleshot_inst2 |
| +++inst_ac_out | | 286/289 | 248/250 | 246/248 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io/inst_ac_out |
| ++++singleshot_inst1 | | 3/3 | 2/2 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io/inst_ac_out/singleshot_inst1 |
| ++inst_tx_fifo | | 1/39 | 0/29 | 1/65 | 0/0 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_tx_fifo |
| +++inst_dpram_1w1r | | 0/0 | 0/0 | 0/0 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_tx_fifo/inst_dpram_1w1r |
| +++inst_fifo_sync_ctrl | | 38/38 | 29/29 | 64/64 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_tx_fifo/inst_fifo_sync_ctrl |
| +inst_clockgen | | 44/50 | 54/54 | 18/24 | 4/10 | 0/0 | 0/0 | 8/8 | 0/0 | 0/0 | 4/4 | mips_sys/inst_clockgen |
| ++Mshreg_reset_pipe0_19_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_clockgen/Mshreg_reset_pipe0_19_0 |
| ++Mshreg_reset_pipe0_19_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_clockgen/Mshreg_reset_pipe0_19_1 |
| ++Mshreg_reset_pipe1_19_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_clockgen/Mshreg_reset_pipe1_19_0 |
| ++Mshreg_reset_pipe1_19_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_clockgen/Mshreg_reset_pipe1_19_1 |
| ++Mshreg_reset_pipe2_19_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_clockgen/Mshreg_reset_pipe2_19_0 |
| ++Mshreg_reset_pipe2_19_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_clockgen/Mshreg_reset_pipe2_19_1 |
| +inst_flash_port | | 80/80 | 65/65 | 54/54 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_flash_port |
| +inst_gpio_wb | | 301/301 | 298/298 | 433/433 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_gpio_wb |
| +inst_mips_top | | 26/2930 | 22/1950 | 12/4222 | 2/611 | 0/27 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top |
| ++Mshreg_reset_delay_15 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/Mshreg_reset_delay_15 |
| ++Mshreg_reset_delay_19 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/Mshreg_reset_delay_19 |
| ++Mshreg_reset_delay_30 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/Mshreg_reset_delay_30 |
| ++inst_biu | | 191/816 | 97/561 | 210/926 | 0/350 | 0/27 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu |
| +++inst_bin_fifo | | 2/97 | 0/62 | 2/106 | 0/74 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo |
| ++++inst_dpram_1w1r | | 57/57 | 32/32 | 64/64 | 64/64 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r |
| ++++inst_fifo_async_ctrl | | 12/38 | 12/30 | 6/40 | 0/10 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl |
| +++++Mshreg_gcnt2_r_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_0 |
| +++++Mshreg_gcnt2_r_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_1 |
| +++++Mshreg_gcnt2_r_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_2 |
| +++++Mshreg_gcnt2_r_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_3 |
| +++++Mshreg_gcnt2_r_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_4 |
| +++++Mshreg_gcnt2_w_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_0 |
| +++++Mshreg_gcnt2_w_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_1 |
| +++++Mshreg_gcnt2_w_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_2 |
| +++++Mshreg_gcnt2_w_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_3 |
| +++++Mshreg_gcnt2_w_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_4 |
| +++++inst_gray_counter_r | | 8/8 | 9/9 | 12/12 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/inst_gray_counter_r |
| +++++inst_gray_counter_w | | 8/8 | 9/9 | 12/12 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/inst_gray_counter_w |
| +++inst_bout_fifo | | 6/150 | 0/97 | 6/177 | 0/144 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo |
| ++++inst_dpram_1w1r | | 105/105 | 67/67 | 134/134 | 134/134 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_dpram_1w1r |
| ++++inst_fifo_async_ctrl | | 10/39 | 12/30 | 3/37 | 0/10 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl |
| +++++Mshreg_gcnt2_r_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_0 |
| +++++Mshreg_gcnt2_r_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_1 |
| +++++Mshreg_gcnt2_r_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_2 |
| +++++Mshreg_gcnt2_r_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_3 |
| +++++Mshreg_gcnt2_r_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_4 |
| +++++Mshreg_gcnt2_w_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_0 |
| +++++Mshreg_gcnt2_w_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_1 |
| +++++Mshreg_gcnt2_w_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_2 |
| +++++Mshreg_gcnt2_w_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_3 |
| +++++Mshreg_gcnt2_w_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_4 |
| +++++inst_gray_counter_r | | 9/9 | 9/9 | 11/11 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/inst_gray_counter_r |
| +++++inst_gray_counter_w | | 10/10 | 9/9 | 13/13 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/inst_gray_counter_w |
| +++inst_dcache | | 174/174 | 147/147 | 149/149 | 0/0 | 0/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_dcache |
| ++++gen_data_ram[0].inst_data_ra | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_dcache/gen_data_ram[0].inst_data_ram |
| ++++gen_data_ram[1].inst_data_ra | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_dcache/gen_data_ram[1].inst_data_ram |
| ++++gen_data_ram[2].inst_data_ra | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_dcache/gen_data_ram[2].inst_data_ram |
| ++++gen_data_ram[3].inst_data_ra | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_dcache/gen_data_ram[3].inst_data_ram |
| ++++inst_tag_ram | | 0/0 | 0/0 | 0/0 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_dcache/inst_tag_ram |
| +++inst_icache | | 117/117 | 81/81 | 123/123 | 0/0 | 0/18 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_icache |
| ++++inst_data_ram | | 0/0 | 0/0 | 0/0 | 0/0 | 16/16 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_icache/inst_data_ram |
| ++++inst_tag_ram | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_icache/inst_tag_ram |
| +++inst_write_fifo | | 2/87 | 0/77 | 2/161 | 0/132 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_write_fifo |
| ++++inst_dpram_1w1r | | 66/66 | 66/66 | 132/132 | 132/132 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_write_fifo/inst_dpram_1w1r |
| ++++inst_fifo_sync_ctrl | | 19/19 | 11/11 | 27/27 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_write_fifo/inst_fifo_sync_ctrl |
| ++inst_cop | | 239/239 | 190/190 | 237/237 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_cop |
| ++inst_pipeline | | 921/1846 | 650/1177 | 1386/3044 | 0/256 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_pipeline |
| +++inst_alu | | 62/62 | 0/0 | 119/119 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_pipeline/inst_alu |
| +++inst_bcu | | 8/8 | 0/0 | 16/16 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_pipeline/inst_bcu |
| +++inst_muldiv | | 572/572 | 527/527 | 1027/1027 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_pipeline/inst_muldiv |
| +++inst_reg_dual | | 128/128 | 0/0 | 256/256 | 256/256 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_pipeline/inst_reg_dual |
| +++inst_shifter | | 155/155 | 0/0 | 240/240 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_pipeline/inst_shifter |
| +inst_ps2_phy_0 | | 0/11 | 0/10 | 0/18 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_phy_0 |
| ++Inst_debounce_clk | | 6/6 | 5/5 | 9/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_phy_0/Inst_debounce_clk |
| ++Inst_debounce_data | | 5/5 | 5/5 | 9/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_phy_0/Inst_debounce_data |
| +inst_ps2_phy_1 | | 0/12 | 0/10 | 0/18 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_phy_1 |
| ++Inst_debounce_clk | | 6/6 | 5/5 | 9/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_phy_1/Inst_debounce_clk |
| ++Inst_debounce_data | | 6/6 | 5/5 | 9/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_phy_1/Inst_debounce_data |
| +inst_ps2_wb_0 | | 35/157 | 30/139 | 23/169 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_wb_0 |
| ++inst_ps2_core | | 122/122 | 109/109 | 146/146 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_wb_0/inst_ps2_core |
| +inst_ps2_wb_1 | | 32/150 | 30/139 | 21/167 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_wb_1 |
| ++inst_ps2_core | | 118/118 | 109/109 | 146/146 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_wb_1/inst_ps2_core |
| +inst_rom_wb | | 1/76 | 1/99 | 1/53 | 0/2 | 0/4 | 0/0 | 0/2 | 0/0 | 0/0 | 0/0 | mips_sys/inst_rom_wb |
| ++inst_rom | | 75/75 | 98/98 | 52/52 | 2/2 | 4/4 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | mips_sys/inst_rom_wb/inst_rom |
| +inst_sdram_ctrl_frontend_wb | | 110/669 | 0/455 | 145/593 | 0/39 | 0/6 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb |
| ++inst_cat_fifo | | 2/17 | 0/13 | 2/23 | 0/0 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_cat_fifo |
| +++inst_dpram_1w1r | | 0/0 | 0/0 | 0/0 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_cat_fifo/inst_dpram_1w1r |
| +++inst_fifo_sync_ctrl | | 15/15 | 13/13 | 21/21 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_cat_fifo/inst_fifo_sync_ctrl |
| ++inst_read_fifo | | 2/54 | 0/36 | 2/54 | 0/12 | 0/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo |
| +++inst_dpram_1w1r | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_dpram_1w1r |
| +++inst_fifo_async_ctrl | | 18/52 | 14/36 | 10/52 | 0/12 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl |
| ++++Mshreg_gcnt2_r_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_0 |
| ++++Mshreg_gcnt2_r_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_1 |
| ++++Mshreg_gcnt2_r_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_2 |
| ++++Mshreg_gcnt2_r_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_3 |
| ++++Mshreg_gcnt2_r_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_4 |
| ++++Mshreg_gcnt2_r_5 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_5 |
| ++++Mshreg_gcnt2_w_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_0 |
| ++++Mshreg_gcnt2_w_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_1 |
| ++++Mshreg_gcnt2_w_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_2 |
| ++++Mshreg_gcnt2_w_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_3 |
| ++++Mshreg_gcnt2_w_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_4 |
| ++++Mshreg_gcnt2_w_5 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_5 |
| ++++inst_gray_counter_r | | 11/11 | 11/11 | 15/15 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/inst_gray_counter_r |
| ++++inst_gray_counter_w | | 11/11 | 11/11 | 15/15 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/inst_gray_counter_w |
| ++inst_sdram_ctrl | | 0/433 | 0/370 | 0/317 | 0/15 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl |
| +++inst_ddr_phy | | 179/180 | 216/216 | 2/3 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy |
| ++++Mshreg_u_tag_pipe_4_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/Mshreg_u_tag_pipe_4_0 |
| +++inst_sd_cmd_fifo | | 4/64 | 0/41 | 6/58 | 0/14 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo |
| ++++inst_dpram_1w1r | | 0/0 | 0/0 | 0/0 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r |
| ++++inst_fifo_async_ctrl | | 21/60 | 17/41 | 9/52 | 0/14 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl |
| +++++Mshreg_gcnt2_r_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_0 |
| +++++Mshreg_gcnt2_r_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_1 |
| +++++Mshreg_gcnt2_r_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_2 |
| +++++Mshreg_gcnt2_r_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_4 |
| +++++Mshreg_gcnt2_r_5 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_5 |
| +++++Mshreg_gcnt2_w_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_0 |
| +++++Mshreg_gcnt2_w_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_1 |
| +++++Mshreg_gcnt2_w_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_2 |
| +++++Mshreg_gcnt2_w_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_3 |
| +++++Mshreg_gcnt2_w_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_4 |
| +++++Mshreg_gcnt2_w_5 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_5 |
| +++++Mshreg_p2_3_BRB0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_p2_3_BRB0 |
| +++++Mshreg_p2_3_BRB1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_p2_3_BRB1 |
| +++++Mshreg_p2_3_BRB2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_p2_3_BRB2 |
| +++++inst_gray_counter_r | | 14/14 | 13/13 | 14/14 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r |
| +++++inst_gray_counter_w | | 11/11 | 11/11 | 15/15 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_w |
| +++inst_sdram_cmd | | 46/46 | 13/13 | 65/65 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd |
| +++inst_sdram_ctrl | | 143/143 | 100/100 | 191/191 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl |
| ++inst_write_fifo | | 3/55 | 0/36 | 3/54 | 0/12 | 0/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo |
| +++inst_dpram_1w1r | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_dpram_1w1r |
| +++inst_fifo_async_ctrl | | 19/52 | 14/36 | 9/51 | 0/12 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl |
| ++++Mshreg_gcnt2_r_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_0 |
| ++++Mshreg_gcnt2_r_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_1 |
| ++++Mshreg_gcnt2_r_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_2 |
| ++++Mshreg_gcnt2_r_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_3 |
| ++++Mshreg_gcnt2_r_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_4 |
| ++++Mshreg_gcnt2_r_5 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_5 |
| ++++Mshreg_gcnt2_w_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_0 |
| ++++Mshreg_gcnt2_w_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_1 |
| ++++Mshreg_gcnt2_w_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_2 |
| ++++Mshreg_gcnt2_w_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_3 |
| ++++Mshreg_gcnt2_w_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_4 |
| ++++Mshreg_gcnt2_w_5 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_5 |
| ++++inst_gray_counter_r | | 10/10 | 11/11 | 15/15 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/inst_gray_counter_r |
| ++++inst_gray_counter_w | | 11/11 | 11/11 | 15/15 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/inst_gray_counter_w |
| +inst_uart_wb_0 | | 59/105 | 64/106 | 43/111 | 0/36 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0 |
| ++inst_uart_rx | | 0/29 | 0/28 | 0/38 | 0/27 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0/inst_uart_rx |
| +++buf | | 8/8 | 5/5 | 16/16 | 8/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0/inst_uart_rx/buf |
| +++kcuart | | 21/21 | 23/23 | 22/22 | 19/19 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0/inst_uart_rx/kcuart |
| ++inst_uart_tx | | 0/17 | 0/14 | 0/30 | 0/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0/inst_uart_tx |
| +++buf | | 8/8 | 5/5 | 16/16 | 8/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0/inst_uart_tx/buf |
| +++kcuart | | 9/9 | 9/9 | 14/14 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0/inst_uart_tx/kcuart |
| +inst_uart_wb_1 | | 56/103 | 64/108 | 42/110 | 0/36 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_1 |
| ++inst_uart_rx | | 0/28 | 0/29 | 0/38 | 0/27 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_1/inst_uart_rx |
| +++buf | | 8/8 | 5/5 | 16/16 | 8/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_1/inst_uart_rx/buf |
| +++kcuart | | 20/20 | 24/24 | 22/22 | 19/19 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_1/inst_uart_rx/kcuart |
| ++inst_uart_tx | | 0/19 | 0/15 | 0/30 | 0/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_1/inst_uart_tx |
| +++buf | | 8/8 | 5/5 | 16/16 | 8/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_1/inst_uart_tx/buf |
| +++kcuart | | 11/11 | 10/10 | 14/14 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_1/inst_uart_tx/kcuart |
| +inst_usb_port | | 37/37 | 27/27 | 31/31 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_usb_port |
| +inst_vga_frontend | | 802/1436 | 793/1251 | 762/1553 | 0/264 | 0/13 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend |
| ++inst_blitfifo | | 4/31 | 0/23 | 4/45 | 0/0 | 0/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_blitfifo |
| +++inst_dpram_1w1r | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_blitfifo/inst_dpram_1w1r |
| +++inst_fifo_sync_ctrl | | 27/27 | 23/23 | 41/41 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl |
| ++inst_bus_fifo | | 3/116 | 0/110 | 3/219 | 0/206 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_bus_fifo |
| +++inst_dpram_1w1r | | 103/103 | 103/103 | 206/206 | 206/206 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_bus_fifo/inst_dpram_1w1r |
| +++inst_fifo_sync_ctrl | | 10/10 | 7/7 | 10/10 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_bus_fifo/inst_fifo_sync_ctrl |
| ++inst_char_gen | | 194/206 | 126/126 | 240/252 | 0/12 | 0/4 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen |
| +++Mshreg_csr_posx_synced_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posx_synced_0 |
| +++Mshreg_csr_posx_synced_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posx_synced_1 |
| +++Mshreg_csr_posx_synced_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posx_synced_2 |
| +++Mshreg_csr_posx_synced_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posx_synced_3 |
| +++Mshreg_csr_posx_synced_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posx_synced_4 |
| +++Mshreg_csr_posx_synced_5 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posx_synced_5 |
| +++Mshreg_csr_posx_synced_6 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posx_synced_6 |
| +++Mshreg_csr_posy_synced_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posy_synced_0 |
| +++Mshreg_csr_posy_synced_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posy_synced_1 |
| +++Mshreg_csr_posy_synced_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posy_synced_2 |
| +++Mshreg_csr_posy_synced_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posy_synced_3 |
| +++Mshreg_csr_posy_synced_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posy_synced_4 |
| +++inst_ascii_ram | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/inst_ascii_ram |
| +++inst_char_rom | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/inst_char_rom |
| ++inst_linefifo | | 2/178 | 0/149 | 2/177 | 0/46 | 0/7 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo |
| +++inst_dpram_1w1r | | 0/0 | 0/0 | 0/0 | 0/0 | 7/7 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_dpram_1w1r |
| +++inst_fifo_async_ctrl | | 83/176 | 91/149 | 81/175 | 0/46 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl |
| ++++Mshreg_bcnt2_ar_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_0 |
| ++++Mshreg_bcnt2_ar_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_1 |
| ++++Mshreg_bcnt2_ar_10 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_10 |
| ++++Mshreg_bcnt2_ar_11 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_11 |
| ++++Mshreg_bcnt2_ar_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_2 |
| ++++Mshreg_bcnt2_ar_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_3 |
| ++++Mshreg_bcnt2_ar_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_4 |
| ++++Mshreg_bcnt2_ar_5 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_5 |
| ++++Mshreg_bcnt2_ar_6 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_6 |
| ++++Mshreg_bcnt2_ar_7 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_7 |
| ++++Mshreg_bcnt2_ar_8 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_8 |
| ++++Mshreg_bcnt2_ar_9 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_9 |
| ++++Mshreg_bcnt2_aw_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_aw_0 |
| ++++Mshreg_bcnt2_aw_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_aw_1 |
| ++++Mshreg_bcnt2_aw_10 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_aw_10 |
| ++++Mshreg_bcnt2_aw_11 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_aw_11 |
| ++++Mshreg_bcnt2_aw_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_aw_2 |
| ++++Mshreg_bcnt2_aw_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_aw_3 |
| ++++Mshreg_bcnt2_aw_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_aw_4 |
| ++++Mshreg_bcnt2_aw_5 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_aw_5 |
| ++++Mshreg_bcnt2_aw_6 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_aw_6 |
| ++++Mshreg_bcnt2_aw_7 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_aw_7 |
| ++++Mshreg_bcnt2_aw_8 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_aw_8 |
| ++++Mshreg_bcnt2_aw_9 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_aw_9 |
| ++++Mshreg_gcnt2_r_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_0 |
| ++++Mshreg_gcnt2_r_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_1 |
| ++++Mshreg_gcnt2_r_10 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_10 |
| ++++Mshreg_gcnt2_r_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_2 |
| ++++Mshreg_gcnt2_r_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_3 |
| ++++Mshreg_gcnt2_r_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_4 |
| ++++Mshreg_gcnt2_r_5 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_5 |
| ++++Mshreg_gcnt2_r_6 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_6 |
| ++++Mshreg_gcnt2_r_7 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_7 |
| ++++Mshreg_gcnt2_r_8 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_8 |
| ++++Mshreg_gcnt2_r_9 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_9 |
| ++++Mshreg_gcnt2_w_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_0 |
| ++++Mshreg_gcnt2_w_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_1 |
| ++++Mshreg_gcnt2_w_10 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_10 |
| ++++Mshreg_gcnt2_w_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_2 |
| ++++Mshreg_gcnt2_w_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_3 |
| ++++Mshreg_gcnt2_w_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_4 |
| ++++Mshreg_gcnt2_w_5 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_5 |
| ++++Mshreg_gcnt2_w_6 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_6 |
| ++++Mshreg_gcnt2_w_7 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_7 |
| ++++Mshreg_gcnt2_w_8 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_8 |
| ++++Mshreg_gcnt2_w_9 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_9 |
| ++++inst_gray_counter_r | | 20/20 | 23/23 | 24/24 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r |
| ++++inst_gray_counter_w | | 27/27 | 35/35 | 24/24 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_w |
| ++inst_vga_backend | | 61/103 | 24/50 | 62/98 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_vga_backend |
| +++inst_vga_timing | | 0/42 | 0/26 | 0/36 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_vga_backend/inst_vga_timing |
| ++++inst_vga_sync_h | | 20/20 | 13/13 | 18/18 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h |
| ++++inst_vga_sync_v | | 22/22 | 13/13 | 18/18 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_v |
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
* Slices can be packed with basic elements from multiple hierarchies.
Therefore, a slice will be counted in every hierarchical module
that each of its packed basic elements belong to.
** For each column, there are two numbers reported <A>/<B>.
<A> is the number of elements that belong to that specific hierarchical module.
<B> is the total number of elements from that hierarchical module and any lower level
hierarchical modules below.
*** The LUTRAM column counts all LUTs used as memory including RAM, ROM, and shift registers.
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