jens
943e7e9388
Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@754 cc03376c-175c-47c8-b038-4cd826a8556b
187 lines
8.5 KiB
Plaintext
187 lines
8.5 KiB
Plaintext
Release 10.1.03 par K.39 (nt)
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Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
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JUPITER:: Sun Feb 14 18:14:54 2010
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par -w -intstyle ise -ol high -xe n -t 1 mips_sys_map.ncd mips_sys.ncd
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mips_sys.pcf
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Constraints file: mips_sys.pcf.
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Loading device for application Rf_Device from file '4vsx35.nph' in environment C:\Programme\Xilinx101\ISE.
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"mips_sys" is an NCD, version 3.2, device xc4vsx35, package ff668, speed -10
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The STEPPING level for this design is ES.
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Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
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Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
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Device speed data version: "PRODUCTION 1.68 2008-07-25".
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Device Utilization Summary:
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Number of BSCANs 1 out of 4 25%
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Number of BUFGs 12 out of 32 37%
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Number of DCM_ADVs 4 out of 8 50%
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Number of ILOGICs 99 out of 448 22%
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Number of External IOBs 226 out of 448 50%
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Number of LOCed IOBs 226 out of 226 100%
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Number of OLOGICs 182 out of 448 40%
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Number of RAMB16s 51 out of 192 26%
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Number of Slices 6008 out of 15360 39%
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Number of SLICEMs 558 out of 7680 7%
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Overall effort level (-ol): High
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Router effort level (-rl): High
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Starting initial Timing Analysis. REAL time: 14 secs
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Finished initial Timing Analysis. REAL time: 14 secs
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Starting Router
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Phase 1: 48218 unrouted; REAL time: 15 secs
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Phase 2: 41114 unrouted; REAL time: 16 secs
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Phase 3: 15775 unrouted; REAL time: 22 secs
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Phase 4: 15775 unrouted; (290927) REAL time: 23 secs
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Phase 5: 16549 unrouted; (7681) REAL time: 26 secs
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Phase 6: 16600 unrouted; (0) REAL time: 26 secs
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Phase 7: 0 unrouted; (942) REAL time: 53 secs
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Updating file: mips_sys.ncd with current fully routed design.
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Phase 8: 0 unrouted; (942) REAL time: 1 mins 14 secs
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Phase 9: 0 unrouted; (942) REAL time: 1 mins 20 secs
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Phase 10: 0 unrouted; (0) REAL time: 1 mins 26 secs
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Phase 11: 0 unrouted; (0) REAL time: 1 mins 27 secs
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Updating file: mips_sys.ncd with current fully routed design.
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Phase 12: 0 unrouted; (0) REAL time: 1 mins 46 secs
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Phase 13: 0 unrouted; (0) REAL time: 1 mins 52 secs
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Total REAL time to Router completion: 1 mins 54 secs
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Total CPU time to Router completion: 1 mins 49 secs
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Partition Implementation Status
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-------------------------------
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No Partitions were found in this design.
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-------------------------------
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Generating "PAR" statistics.
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**************************
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Generating Clock Report
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**************************
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+---------------------+--------------+------+------+------------+-------------+
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| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
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+---------------------+--------------+------+------+------------+-------------+
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| cpu_clk |BUFGCTRL_X0Y12| No | 1638 | 0.443 | 4.049 |
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+---------------------+--------------+------+------+------------+-------------+
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| CLK_O | BUFGCTRL_X0Y2| No | 2331 | 0.533 | 3.922 |
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+---------------------+--------------+------+------+------------+-------------+
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| vga_clk |BUFGCTRL_X0Y11| No | 167 | 0.287 | 3.881 |
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+---------------------+--------------+------+------+------------+-------------+
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|inst_rom_wb/inst_rom | | | | | |
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| /bs_clk1 | BUFGCTRL_X0Y0| No | 75 | 0.416 | 3.851 |
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+---------------------+--------------+------+------+------------+-------------+
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| sdram_clk0 |BUFGCTRL_X0Y31| No | 241 | 0.494 | 3.933 |
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+---------------------+--------------+------+------+------------+-------------+
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|sys_ac97_bit_clk_IBU | | | | | |
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| F | BUFGCTRL_X0Y8| No | 251 | 0.356 | 3.903 |
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+---------------------+--------------+------+------+------------+-------------+
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| sys_clk_in_IBUFG | BUFGCTRL_X0Y1| No | 62 | 0.223 | 3.686 |
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+---------------------+--------------+------+------+------------+-------------+
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| sdram_clk270 |BUFGCTRL_X0Y16| No | 65 | 0.160 | 3.932 |
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+---------------------+--------------+------+------+------------+-------------+
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| sdram_clk270var |BUFGCTRL_X0Y28| No | 32 | 0.025 | 3.930 |
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+---------------------+--------------+------+------+------------+-------------+
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|inst_rom_wb/inst_rom | | | | | |
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| /bs_update1 |BUFGCTRL_X0Y26| No | 4 | 0.146 | 3.628 |
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+---------------------+--------------+------+------+------------+-------------+
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* Net Skew is the difference between the minimum and maximum routing
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only delays for the net. Note this is different from Clock Skew which
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is reported in TRCE timing report. Clock Skew is the difference between
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the minimum and maximum path delays which includes logic delays.
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Timing Score: 0
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INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no
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requested value.
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Asterisk (*) preceding a constraint indicates it was not met.
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This may be due to a setup or hold violation.
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------------------------------------------------------------------------------------------------------
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Constraint | Check | Worst Case | Best Case | Timing | Timing
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| | Slack | Achievable | Errors | Score
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------------------------------------------------------------------------------------------------------
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TS_cpu_clk = PERIOD TIMEGRP "cpu_clk" 9.9 | SETUP | 0.018ns| 9.864ns| 0| 0
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ns HIGH 50% | HOLD | 0.314ns| | 0| 0
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------------------------------------------------------------------------------------------------------
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TS_sdram_clk = PERIOD TIMEGRP "sdram_clk" | SETUP | 0.054ns| 7.392ns| 0| 0
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7.5 ns HIGH 50% | HOLD | 0.518ns| | 0| 0
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------------------------------------------------------------------------------------------------------
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TS_vga_clk = PERIOD TIMEGRP "vga_clk" 8 n | SETUP | 0.109ns| 7.891ns| 0| 0
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s HIGH 50% | HOLD | 0.480ns| | 0| 0
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------------------------------------------------------------------------------------------------------
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TS_clk = PERIOD TIMEGRP "sys_clk" 9.9 ns | SETUP | 0.166ns| 9.734ns| 0| 0
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HIGH 50% | HOLD | 0.333ns| | 0| 0
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------------------------------------------------------------------------------------------------------
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NET "sys_ac97_bit_clk_IBUF1" PERIOD = 80 | SETUP | 35.896ns| 8.208ns| 0| 0
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ns HIGH 50% | HOLD | 0.518ns| | 0| 0
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------------------------------------------------------------------------------------------------------
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TSACBITCLK = PERIOD TIMEGRP "ac97_clk" 80 | SETUP | 75.311ns| 4.689ns| 0| 0
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ns HIGH 50% | HOLD | 0.783ns| | 0| 0
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------------------------------------------------------------------------------------------------------
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PATH "TS_unrelate_SDRAM_path" TIG | SETUP | N/A| 9.588ns| N/A| 0
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------------------------------------------------------------------------------------------------------
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PATH "TS_unrelate_VGA_path" TIG | SETUP | N/A| 6.296ns| N/A| 0
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------------------------------------------------------------------------------------------------------
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All constraints were met.
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INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
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constraint does not cover any paths or that it has no requested value.
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Generating Pad Report.
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All signals are completely routed.
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Total REAL time to PAR completion: 2 mins 3 secs
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Total CPU time to PAR completion: 1 mins 55 secs
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Peak Memory Usage: 453 MB
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Placer: Placement generated during map.
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Routing: Completed - No errors found.
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Timing: Completed - No errors found.
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Number of error messages: 0
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Number of warning messages: 0
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Number of info messages: 1
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Writing design to file mips_sys.ncd
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PAR done!
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