jens
c1e96aecba
- use main_sim for test bench git-svn-id: http://moon:8086/svn/vhdl/trunk@1576 cc03376c-175c-47c8-b038-4cd826a8556b
27 lines
851 B
Makefile
27 lines
851 B
Makefile
# -----------------------------------------------------------
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include $(VHDL_HOME)/make/defs.mk
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# -----------------------------------------------------------
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include $(LIB_PATH)/VGA_ctrl/ghdl/vga_backend.inc
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include $(LIB_PATH)/FIFO/ghdl/fifo_async.inc
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include $(LIB_PATH)/CPUs/JCpu/ghdl/jcpu_core.inc
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# -----------------------------------------------------------
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SRCS += $(VGA_BACKEND_SRCS)
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SRCS += $(FIFO_ASYNC_SRCS)
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SRCS += $(JCPU_CORE_SRCS)
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SRCS += ../src/sim/main_sim_xrom.vhdl
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SRCS += ../src/sim/main_sim_irom.vhdl
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SRCS += ../src/cpu_embedded.vhd
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SRCS += ../src/vga_ctrl_top.vhd
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SRCS += ../src/tb_vga_ctrl.vhd
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# -----------------------------------------------------------
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# Compile
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TARGET := tb_vga_ctrl
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ENTITY := tb_vga_ctrl
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RUN_TIME := 2500us
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include $(VHDL_HOME)/make/ghdl.mk
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# -----------------------------------------------------------
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