jens
d7ed0a9fb0
git-svn-id: http://moon:8086/svn/vhdl/trunk@183 cc03376c-175c-47c8-b038-4cd826a8556b
384 lines
11 KiB
VHDL
384 lines
11 KiB
VHDL
--------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 17:16:42 13.05.2007
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-- Design Name: tb_nco
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-- Module Name: tb_nco.vhd
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-- Project Name: nco
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.MATH_REAL.ALL;
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USE ieee.numeric_std.ALL;
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use std.textio.all; -- Imports the standard textio package.
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library ieee_proposed;
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use ieee_proposed.math_utility_pkg.all;
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use ieee_proposed.fixed_pkg.all;
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library work;
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use work.fixed_util_pkg.all;
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use work.cordic_pkg.all;
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use work.PCK_FIO.all;
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ENTITY tb_ddc IS
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Generic
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(
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nbits_in : integer := 16;
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nbits_in_frac : integer := 14;
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nbits_out : integer := 24;
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nbits_out_frac : integer := 22;
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lo_nbits_phase : integer := 20;
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lo_nbits_freq : integer := 20;
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cic_nstages : integer := 3;
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cic_ratio : integer := 50;
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cic_scale_nbits : integer := 16;
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rfgen_nbits_phase : integer := 20;
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rfgen_nbits_freq : integer := 20
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);
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END tb_ddc;
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ARCHITECTURE behavior OF tb_ddc IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT ddc
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GENERIC
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(
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nbits_in : integer;
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nbits_in_frac : integer;
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nbits_out : integer;
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nbits_out_frac : integer;
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lo_nbits_phase : integer;
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lo_nbits_freq : integer;
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cic_nstages : integer;
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cic_ratio : integer;
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cic_scale_nbits : integer
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);
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PORT
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(
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rst : in std_logic;
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clk : in std_logic;
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lo_nco_rst : in std_logic;
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lo_nco_en : in std_logic;
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lo_freq_in : in unsigned(lo_nbits_freq-1 downto 0);
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lo_phase_in : in unsigned(lo_nbits_phase-1 downto 0);
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din_i : in sfixed;
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din_q : in sfixed;
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din_vld : in std_logic;
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-- dec_i : out sfixed;
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-- dec_q : out sfixed;
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-- dec_vld : out std_logic;
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dout_i : out sfixed;
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dout_q : out sfixed;
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dout_vld : out std_logic
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);
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END COMPONENT;
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-- Rf-Generator
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COMPONENT mix
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GENERIC
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(
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nbits_din : integer;
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nbits_din_frac : integer;
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nbits_dout : integer;
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nbits_dout_frac : integer;
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nbits_phase : integer;
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nbits_freq : integer
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);
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PORT
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(
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rst : in std_logic;
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clk : in std_logic;
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nco_rst : in std_logic;
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nco_en : in std_logic;
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freq_in : in unsigned(nbits_freq-1 downto 0);
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phase_in : in unsigned(nbits_phase-1 downto 0);
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din_i : in sfixed;
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din_q : in sfixed;
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dout_i : out sfixed;
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dout_q : out sfixed;
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din_vld : in std_logic;
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dout_vld : out std_logic
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);
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END COMPONENT;
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--Constants
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constant fa : REAL := 100.0E6;
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constant frf1 : REAL := 29.9E6;
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constant frf2 : REAL := 30.0E6;
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constant frf3 : REAL := 30.1E6;
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constant flo : REAL := 30.0E6;
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constant PERIOD : time := 10 ns;
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SIGNAL rfgen1_freq_word : integer := integer(frf1/fa*2.0**rfgen_nbits_freq);
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SIGNAL rfgen2_freq_word : integer := integer(frf2/fa*2.0**rfgen_nbits_freq);
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SIGNAL rfgen3_freq_word : integer := integer(frf3/fa*2.0**rfgen_nbits_freq);
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SIGNAL lo_freq_word : integer := integer(flo/fa*2.0**lo_nbits_freq);
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--Inputs
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SIGNAL clk : std_logic := '0';
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SIGNAL rst : std_logic := '1';
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SIGNAL ddc_nco_rst : std_logic := '0';
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SIGNAL ddc_nco_en : std_logic := '0';
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SIGNAL ddc_freq_in : unsigned(lo_nbits_freq-1 downto 0) := (others => '0');
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SIGNAL ddc_phase_in : unsigned(lo_nbits_phase-1 downto 0) := (others => '0');
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--Outputs
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SIGNAL ddc_din_i : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
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SIGNAL ddc_din_q : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
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SIGNAL ddc_din_vld : std_logic := '0';
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SIGNAL ddc_dec_i : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
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SIGNAL ddc_dec_q : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
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SIGNAL ddc_dec_vld : std_logic;
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SIGNAL ddc_dout_i : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
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SIGNAL ddc_dout_q : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
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SIGNAL ddc_dout_vld : std_logic;
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SIGNAL rfgen_nco_rst : std_logic := '0';
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SIGNAL rfgen_nco_en : std_logic := '0';
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SIGNAL rfgen1_freq_in : unsigned(rfgen_nbits_freq-1 downto 0) := (others => '0');
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SIGNAL rfgen1_phase_in : unsigned(rfgen_nbits_phase-1 downto 0) := (others => '0');
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SIGNAL rfgen2_freq_in : unsigned(rfgen_nbits_freq-1 downto 0) := (others => '0');
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SIGNAL rfgen2_phase_in : unsigned(rfgen_nbits_phase-1 downto 0) := (others => '0');
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SIGNAL rfgen3_freq_in : unsigned(rfgen_nbits_freq-1 downto 0) := (others => '0');
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SIGNAL rfgen3_phase_in : unsigned(rfgen_nbits_phase-1 downto 0) := (others => '0');
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--Outputs
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signal rfgen_din_i : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac)) := to_sfixed(0.0, shi(nbits_in, nbits_in_frac), slo(nbits_in, nbits_in_frac));
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signal rfgen_din_q : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac)) := to_sfixed(1.0, shi(nbits_in, nbits_in_frac), slo(nbits_in, nbits_in_frac));
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SIGNAL rfgen_dout_i : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
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SIGNAL rfgen_dout_q : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
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SIGNAL rfgen1_dout_i : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
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SIGNAL rfgen1_dout_q : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
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SIGNAL rfgen1_dout_vld : std_logic;
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SIGNAL rfgen2_dout_i : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
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SIGNAL rfgen2_dout_q : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
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SIGNAL rfgen2_dout_vld : std_logic;
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SIGNAL rfgen3_dout_i : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
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SIGNAL rfgen3_dout_q : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
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SIGNAL rfgen3_dout_vld : std_logic;
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SIGNAL fileout_enable : std_logic := '0';
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-- Debug
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signal ddc_i_out_f : real;
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signal ddc_q_out_f : real;
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signal rfgen_i_out_f : real;
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signal rfgen_q_out_f : real;
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut : ddc
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GENERIC MAP
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(
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nbits_in => nbits_in,
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nbits_in_frac => nbits_in_frac,
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nbits_out => nbits_out,
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nbits_out_frac => nbits_out_frac,
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lo_nbits_phase => lo_nbits_phase,
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lo_nbits_freq => lo_nbits_freq,
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cic_nstages => cic_nstages,
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cic_ratio => cic_ratio,
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cic_scale_nbits => cic_scale_nbits
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)
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PORT MAP
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(
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rst => rst,
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clk => clk,
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lo_nco_rst => ddc_nco_rst,
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lo_nco_en => ddc_nco_en,
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lo_freq_in => ddc_freq_in,
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lo_phase_in => ddc_phase_in,
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din_i => ddc_din_i,
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din_q => ddc_din_q,
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din_vld => ddc_din_vld,
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-- dec_i => ddc_dec_i,
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-- dec_q => ddc_dec_q,
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-- dec_vld => ddc_dec_vld,
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dout_i => ddc_dout_i,
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dout_q => ddc_dout_q,
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dout_vld => ddc_dout_vld
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);
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rfgen1: mix
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GENERIC MAP
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(
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nbits_din => nbits_in,
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nbits_din_frac => nbits_in_frac,
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nbits_dout => nbits_in,
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nbits_dout_frac => nbits_in_frac,
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nbits_phase => rfgen_nbits_phase,
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nbits_freq => rfgen_nbits_freq
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)
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PORT MAP
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(
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rst => rst,
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clk => clk,
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nco_rst => rfgen_nco_rst,
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nco_en => rfgen_nco_en,
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freq_in => rfgen1_freq_in,
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phase_in => rfgen1_phase_in,
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din_i => rfgen_din_i,
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din_q => rfgen_din_q,
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dout_i => rfgen1_dout_i,
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dout_q => rfgen1_dout_q,
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din_vld => '1',
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dout_vld => rfgen1_dout_vld
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);
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rfgen2: mix
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GENERIC MAP
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(
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nbits_din => nbits_in,
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nbits_din_frac => nbits_in_frac,
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nbits_dout => nbits_in,
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nbits_dout_frac => nbits_in_frac,
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nbits_phase => rfgen_nbits_phase,
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nbits_freq => rfgen_nbits_freq
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)
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PORT MAP
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(
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rst => rst,
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clk => clk,
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nco_rst => rfgen_nco_rst,
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nco_en => rfgen_nco_en,
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freq_in => rfgen2_freq_in,
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phase_in => rfgen2_phase_in,
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din_i => rfgen_din_i,
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din_q => rfgen_din_q,
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dout_i => rfgen2_dout_i,
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dout_q => rfgen2_dout_q,
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din_vld => '1',
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dout_vld => rfgen2_dout_vld
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);
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rfgen3: mix
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GENERIC MAP
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(
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nbits_din => nbits_in,
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nbits_din_frac => nbits_in_frac,
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nbits_dout => nbits_in,
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nbits_dout_frac => nbits_in_frac,
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nbits_phase => rfgen_nbits_phase,
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nbits_freq => rfgen_nbits_freq
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)
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PORT MAP
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(
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rst => rst,
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clk => clk,
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nco_rst => rfgen_nco_rst,
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nco_en => rfgen_nco_en,
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freq_in => rfgen3_freq_in,
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phase_in => rfgen3_phase_in,
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din_i => rfgen_din_i,
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din_q => rfgen_din_q,
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dout_i => rfgen3_dout_i,
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dout_q => rfgen3_dout_q,
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din_vld => '1',
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dout_vld => rfgen3_dout_vld
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);
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tb_clk : PROCESS
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BEGIN
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clk <= not clk;
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wait for PERIOD/2;
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END PROCESS;
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rfgen_dout_i <= resize(0.333*rfgen1_dout_i + 0.333*rfgen2_dout_i + 0.333*rfgen3_dout_i, rfgen_dout_i);
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rfgen_dout_q <= resize(0.333*rfgen1_dout_q + 0.333*rfgen2_dout_q + 0.333*rfgen3_dout_q, rfgen_dout_q);
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ddc_din_i <= rfgen_dout_i;
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ddc_din_q <= to_sfixed(0.0, ddc_din_q);
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ddc_din_vld <= rfgen1_dout_vld and rfgen2_dout_vld and rfgen3_dout_vld;
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ddc_i_out_f <= to_real(ddc_dout_i);
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ddc_q_out_f <= to_real(ddc_dout_q);
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rfgen_i_out_f <= to_real(rfgen_dout_i);
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rfgen_q_out_f <= to_real(rfgen_dout_q);
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tb : PROCESS
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file RESULT_FREQ: text open write_mode is "ratio.txt";
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variable L: line;
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BEGIN
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-- Wait 100 ns for global reset to finish
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wait for 4*PERIOD;
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rst <= '0';
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fprint(RESULT_FREQ, L,"%s\n", natural'image(cic_ratio));
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wait for 2*PERIOD;
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-------------------------------------------
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-- Program gains
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wait for 2*PERIOD;
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wait until rising_edge(clk);
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-- start DDC
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ddc_phase_in <= to_unsigned(0,lo_nbits_phase);
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ddc_freq_in <= to_unsigned(lo_freq_word,lo_nbits_freq);
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wait until rising_edge(clk);
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ddc_nco_en <= '1';
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wait for 20*PERIOD;
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fileout_enable <= '1';
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wait;
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END PROCESS;
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rfgen_ctrl : PROCESS
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BEGIN
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wait until rising_edge(clk) and rst = '0';
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rfgen1_freq_in <= to_unsigned(rfgen1_freq_word,rfgen_nbits_freq);
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rfgen1_phase_in <= to_unsigned(0,rfgen_nbits_phase);
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rfgen2_freq_in <= to_unsigned(rfgen2_freq_word,rfgen_nbits_freq);
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rfgen2_phase_in <= to_unsigned(0,rfgen_nbits_phase);
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rfgen3_freq_in <= to_unsigned(rfgen3_freq_word,rfgen_nbits_freq);
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rfgen3_phase_in <= to_unsigned(0,rfgen_nbits_phase);
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wait until rising_edge(clk);
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rfgen_nco_en <= '1';
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wait;
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END PROCESS;
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tb_fo : PROCESS(clk)
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file RESULT_Ii: text open write_mode is "i_in.txt";
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file RESULT_Qi: text open write_mode is "q_in.txt";
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file RESULT_Ifir: text open write_mode is "i_fir.txt";
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file RESULT_Qfir: text open write_mode is "q_fir.txt";
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file RESULT_Idec: text open write_mode is "i_dec.txt";
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file RESULT_Qdec: text open write_mode is "q_dec.txt";
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variable L: line;
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BEGIN
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if rising_edge(clk) and fileout_enable = '1' then
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if ddc_din_vld = '1' then
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fprint(RESULT_Ii, L,"%s\n", REAL'image(to_real(rfgen_dout_i)));
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fprint(RESULT_Qi, L,"%s\n", REAL'image(to_real(rfgen_dout_q)));
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end if;
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if ddc_dout_vld = '1' then
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fprint(RESULT_Ifir, L,"%s\n", REAL'image(to_real(ddc_dout_i)));
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fprint(RESULT_Qfir, L,"%s\n", REAL'image(to_real(ddc_dout_q)));
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end if;
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if ddc_dec_vld = '1' then
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fprint(RESULT_Idec, L,"%s\n", REAL'image(to_real(ddc_dec_i)));
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fprint(RESULT_Qdec, L,"%s\n", REAL'image(to_real(ddc_dec_q)));
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end if;
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end if;
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END PROCESS;
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END;
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