124 lines
3.5 KiB
VHDL
124 lines
3.5 KiB
VHDL
--------------------------------------------------------------------------
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-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
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-- This file: On-Chip registers
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--
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-- Copyright (C) 2007 J. Ahrensfeld
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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-- For questions and ideas, please contact the author at jens@jayfield.org
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--
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--------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.numeric_std.ALL;
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use work.cpu_pkg.all;
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entity chipreg is
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Port (
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rst : in STD_LOGIC;
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clk : in STD_LOGIC;
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we : in STD_LOGIC;
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addr : in dmem_addr_t;
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din : in dmem_data_t;
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dout : out dmem_data_t;
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ctrl_in : in creg_ctrl_in_t;
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ctrl_out : out creg_ctrl_out_t
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);
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end chipreg;
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architecture Behavioral of chipreg is
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signal reg_page_sel : page_sel_t;
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signal reg_int_ctrl : int_ctrl_in_t;
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signal reg_stk_high : unsigned(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0);
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signal reg_cmem_high : unsigned(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0);
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begin
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proc_assign_ctrl_lines:
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process (clk)
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begin
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if rising_edge(clk) then
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ctrl_out.page_sel <= reg_page_sel;
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ctrl_out.int_ctrl <= reg_int_ctrl;
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ctrl_out.stk_high <= reg_stk_high;
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ctrl_out.cmem_high <= reg_cmem_high;
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end if;
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end process;
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proc_reg_write:
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process (rst, clk)
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begin
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if rst = '1' then
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reg_stk_high <= (others => '0');
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reg_cmem_high <= (others => '0');
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reg_page_sel <= (others => '0');
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reg_int_ctrl.enable <= '0';
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reg_int_ctrl.polarity <= '1';
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reg_int_ctrl.edge_sens <= '1';
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elsif rising_edge(clk) then
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reg_int_ctrl.request <= '0';
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if we = '1' then
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case addr is
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when X"01" =>
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reg_page_sel(page_sel_t'range) <= din(page_sel_t'range);
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when X"03" =>
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reg_int_ctrl.enable <= din(0);
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reg_int_ctrl.polarity <= din(1);
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reg_int_ctrl.edge_sens <= din(2);
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reg_int_ctrl.request <= din(7);
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when X"04" =>
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reg_cmem_high <= din(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0);
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when X"05" =>
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reg_stk_high <= din(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0);
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when others => null;
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end case;
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end if;
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end if;
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end process;
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proc_reg_read:
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process (clk)
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begin
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if rising_edge(clk) then
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case addr is
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when X"00" => -- Revison
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dout <= to_unsigned(REVISION, dmem_data_t'length);
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when X"01" => -- Control 0
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dout <= (7 downto page_sel_t'length => '0') & reg_page_sel;
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when X"02" => -- CPU status
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dout <= "000000" & ctrl_in.alu.carry & ctrl_in.alu.zero;
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when X"03" => -- Interrupt control
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dout <= "00000" & reg_int_ctrl.edge_sens & reg_int_ctrl.polarity & reg_int_ctrl.enable;
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when X"04" => -- Upper stack bits out
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dout <= "0000" & reg_cmem_high;
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when X"05" => -- Upper cmem bits out
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dout <= "0000" & reg_stk_high;
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when others =>
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if addr(0) = '0' then
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dout <= X"DE";
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else
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dout <= X"AD";
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end if;
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end case;
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end if;
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end process;
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end Behavioral;
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