jens
bdb8fec295
git-svn-id: http://moon:8086/svn/vhdl/trunk@1424 cc03376c-175c-47c8-b038-4cd826a8556b
105 lines
3.5 KiB
VHDL
105 lines
3.5 KiB
VHDL
--------------------------------------------------------------------------
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--
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-- Copyright (C) 1993, Peter J. Ashenden
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-- Mail: Dept. Computer Science
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-- University of Adelaide, SA 5005, Australia
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-- e-mail: petera@cs.adelaide.edu.au
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 1, or (at your option)
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-- any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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--
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--------------------------------------------------------------------------
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--
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-- $RCSfile: dlx_test-bench.vhdl,v $ $Revision: 2.1 $ $Date: 1993/10/31 22:40:43 $
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--
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--------------------------------------------------------------------------
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--
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-- Architecture for test bench for DLX,
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-- consisting of clock generator, memory and bus_monitor
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--
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use std.textio.all,
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work.dlx_types.all, work.mem_types.all;
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architecture bench of dlx_test is
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component clock_gen
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port (phi1, phi2 : out bit;
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reset : out bit);
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end component;
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component memory
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port (phi1, phi2 : in bit;
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a : in dlx_address;
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d : inout dlx_word_bus bus;
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width : in mem_width;
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write_enable : in bit;
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burst : in bit := '0';
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mem_enable : in bit;
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ready : out bit);
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end component;
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component dlx
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port (phi1, phi2 : in bit; -- 2-phase non-overlapping clocks
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reset : in bit; -- synchronous reset input
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a : out dlx_address; -- address bus output
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d : inout dlx_word_bus bus; -- bidirectional data bus
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halt : out bit; -- halt indicator
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width : out mem_width; -- byte/haldword/word indicator
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write_enable : out bit; -- selects read or write cycle
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mem_enable : out bit; -- starts memory cycle
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ifetch : out bit; -- indicates instruction fetch
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ready : in bit); -- status from memory system
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end component;
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component dlx_bus_monitor
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port (phi1, phi2 : in bit; -- 2-phase non-overlapping clocks
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reset : in bit; -- synchronous reset
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a : in dlx_address; -- address bus
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d : in dlx_word; -- data bus
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halt : in bit; -- halt indicator
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width : in mem_width; -- byte/haldword/word indicator
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write_enable : in bit; -- selects read or write cycle
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burst : in bit := '0'; -- indicates more to come in burst
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mem_enable : in bit; -- starts memory cycle
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ifetch : in bit; -- indicates instruction fetch
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ready : in bit); -- status from memory system
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end component;
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signal phi1, phi2, reset : bit;
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signal a : dlx_address;
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signal d : dlx_word_bus bus;
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signal halt : bit;
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signal width : mem_width;
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signal write_enable, mem_enable, ifetch, ready : bit;
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begin
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cg : clock_gen
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port map (phi1, phi2, reset);
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mem : memory
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port map (phi1, phi2, a, d, width, write_enable, open, mem_enable, ready);
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proc : dlx
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port map (phi1, phi2, reset, a, d,
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halt, width, write_enable, mem_enable, ifetch, ready);
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bus_monitor : dlx_bus_monitor
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port map (phi1, phi2, reset, a, d,
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halt, width, write_enable, open, mem_enable, ifetch, ready);
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end bench;
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