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d185bd4aa1302826c2ddcfc4845713f59611760c
vhdl/projects/mips_sys/src/mips_sys.vhd
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jens d185bd4aa1 - bugfix 
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git-svn-id: http://moon:8086/svn/vhdl/trunk@742 cc03376c-175c-47c8-b038-4cd826a8556b
2010-02-09 10:21:14 +00:00

1092 lines
28 KiB
VHDL
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-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: system test using Xilinx ML-402
-- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
use std.textio.all; -- Imports the standard textio package.
Library UNISIM;
use UNISIM.vcomponents.all;
library work;
use work.mips_types.all;
use work.sdram_config.all;
use work.sdram_types.all;
use work.vga_types.all;
use work.async_types.all;
use work.async_defs.all;
ENTITY mips_sys IS
GENERIC
(
sys_freq_in : real := 100.0;
sys_freq : real := 100.0;
sdram_phaseshift : integer := 0;
tsvga : vga_timespec_t := ts_vga_800_600_60
);
PORT
(
sys_rst_n_in : in std_logic;
sys_clk_in : in std_logic;
-- Buttons and LEDs
sys_btn : in unsigned(4 downto 0);
sys_dip : in unsigned(7 downto 0);
sys_led : out unsigned(8 downto 0);
-- UART
sys_uart0_rx : in std_logic;
sys_uart0_tx : out std_logic;
sys_uart1_rx : in std_logic;
sys_uart1_tx : out std_logic;
sys_uart2_rx : in std_logic;
sys_uart2_tx : out std_logic;
sys_uart3_rx : in std_logic;
sys_uart3_tx : out std_logic;
-- LCD
sys_lcd_d : inout unsigned(3 downto 0);
sys_lcd_e : out std_logic;
sys_lcd_rs : out std_logic;
sys_lcd_rw : out std_logic;
-- DDR SDRAM
sys_sdr_clk_p : out std_logic; -- ddr_sdram_clock
sys_sdr_clk_n : out std_logic; -- /ddr_sdram_clock
sys_sdr_cke_q : out std_logic; -- clock enable
sys_sdr_cs_qn : out std_logic; -- /chip select
sys_sdr_ras_qn : out std_logic; -- /ras
sys_sdr_cas_qn : out std_logic; -- /cas
sys_sdr_we_qn : out std_logic; -- /write enable
sys_sdr_dm_q : out unsigned(DDR_DM_WIDTH-1 downto 0); -- data mask bits, set to "00"
sys_sdr_dqs_q : inout unsigned(DDR_DQS_WIDTH-1 downto 0); -- data strobe, only for write
sys_sdr_ba_q : out unsigned(DDR_BANK_WIDTH-1 downto 0); -- bank select
sys_sdr_a_q : out unsigned(DDR_ADDR_WIDTH-1 downto 0); -- address bus
sys_sdr_data : inout unsigned(DDR_DATA_WIDTH-1 downto 0); -- bidir data bus
sys_sdr_clk_fb : in std_logic;
-- VGA
sys_vga_clk : out std_logic;
sys_vga_red : out unsigned(7 downto 0);
sys_vga_green : out unsigned(7 downto 0);
sys_vga_blue : out unsigned(7 downto 0);
sys_vga_blank_n : out std_logic;
sys_vga_sync_n : out std_logic;
sys_vga_hsync : out std_logic;
sys_vga_vsync : out std_logic;
sys_usb_d : inout unsigned(15 downto 0);
sys_usb_a : out unsigned(1 downto 0);
sys_usb_csn : out std_logic;
sys_usb_wrn : out std_logic;
sys_usb_rdn : out std_logic;
sys_usb_rstn : out std_logic;
sys_usb_int : in std_logic;
sys_flash_d : inout unsigned(31 downto 0);
sys_flash_a : out unsigned(24 downto 0);
sys_flash_ce : out std_logic;
sys_flash_wrn : out std_logic;
sys_flash_rdn : out std_logic;
sys_flash_ac97_rstn : out std_logic;
sys_flash_byten : out std_logic;
sys_ac97_sdata_in : in std_logic;
sys_ac97_bit_clk : in std_logic;
sys_ac97_sdata_out : out std_logic;
sys_ac97_ssync : out std_logic;
sys_ps2_0_clk : inout std_logic;
sys_ps2_0_data : inout std_logic;
sys_ps2_1_clk : inout std_logic;
sys_ps2_1_data : inout std_logic;
sys_error : out unsigned(1 downto 0) -- indicates Errors
);
-- attribute BUFFER_TYPE : string;
-- attribute BUFFER_TYPE of sys_clk_in : signal is "BUFG";
-- attribute BUFFER_TYPE of sys_sdr_dcm_clk_fb : signal is "BUFG";
END mips_sys;
ARCHITECTURE behavior OF mips_sys IS
COMPONENT mips_top
Port
(
debug : out unsigned(1 downto 0);
eb : in STD_LOGIC;
nmi : in STD_LOGIC;
cpu_clk : in STD_LOGIC;
RST_I : in STD_LOGIC;
CLK_I : in STD_LOGIC;
ACK_I : in STD_LOGIC;
SRDY_I : in STD_LOGIC;
ADDR_O : out word_t;
DAT_I : in word_t;
DAT_O : out word_t;
WE_O : out STD_LOGIC;
SEL_O : out unsigned(3 downto 0);
CYC_O : out STD_LOGIC;
STB_O : out STD_LOGIC;
MRDY_O : out STD_LOGIC;
INT : in unsigned (5 downto 0)
);
END COMPONENT;
COMPONENT rom_wb
PORT
(
CLK_I : in STD_LOGIC;
RST_I : in STD_LOGIC;
CYC_I : in STD_LOGIC;
STB_I : in STD_LOGIC;
ACK_O : out STD_LOGIC;
MRDY_I : in STD_LOGIC;
SRDY_O : out STD_LOGIC;
ADDR_I : in unsigned(31 downto 0);
DAT_O : out unsigned(31 downto 0)
);
END COMPONENT;
COMPONENT lcd_port
PORT
(
rst : in std_logic;
clk : in std_logic;
we : in std_logic;
din : in unsigned(7 downto 0);
dout : out unsigned(7 downto 0);
lcd_d : inout unsigned(3 downto 0);
lcd_e : out std_logic;
lcd_rs : out std_logic;
lcd_rw : out std_logic
);
END COMPONENT;
COMPONENT async_port_wb
GENERIC
(
f_sysclk : real := sys_freq;
addr_width : natural := 32;
data_width : natural := 32;
byte_sel_width : natural := 4;
async_timespec : async_timespec_t
);
PORT
(
CLK_I : in STD_LOGIC;
RST_I : in STD_LOGIC;
CYC_I : in STD_LOGIC;
STB_I : in STD_LOGIC;
WE_I : in STD_LOGIC;
ACK_O : out STD_LOGIC;
SRDY_O : out STD_LOGIC;
MRDY_I : in STD_LOGIC;
SEL_I : in unsigned(3 downto 0);
ADDR_I : in unsigned(31 downto 0);
DAT_I : in unsigned(31 downto 0);
DAT_O : out unsigned(31 downto 0);
page_mode_en : in STD_LOGIC;
async_a : out unsigned(addr_width-1 downto 0);
async_d : inout unsigned(data_width-1 downto 0);
async_cs : out std_logic;
async_wr : out std_logic;
async_rd : out std_logic;
async_be : out unsigned(byte_sel_width-1 downto 0);
async_rst : out std_logic
);
END COMPONENT;
COMPONENT uart_wb
PORT
(
CLK_I : in STD_LOGIC;
RST_I : in STD_LOGIC;
CYC_I : in STD_LOGIC;
STB_I : in STD_LOGIC;
SEL_I : in unsigned(3 downto 0);
WE_I : in STD_LOGIC;
ACK_O : out STD_LOGIC;
SRDY_O : out STD_LOGIC;
MRDY_I : in STD_LOGIC;
ADDR_I : in unsigned(31 downto 0);
DAT_I : in unsigned(31 downto 0);
DAT_O : out unsigned(31 downto 0);
INT_O : out STD_LOGIC;
ser_rx : in std_logic;
ser_tx : out std_logic
);
END COMPONENT;
COMPONENT gpio_wb
Generic
(
f_sysclk : real := sys_freq
);
PORT
(
CLK_I : in STD_LOGIC;
RST_I : in STD_LOGIC;
CYC_I : in STD_LOGIC;
STB_I : in STD_LOGIC;
SEL_I : in unsigned(3 downto 0);
WE_I : in STD_LOGIC;
ACK_O : out STD_LOGIC;
SRDY_O : out STD_LOGIC;
MRDY_I : in STD_LOGIC;
ADDR_I : in unsigned(31 downto 0);
DAT_I : in unsigned(31 downto 0);
DAT_O : out unsigned(31 downto 0);
INT_TIM_O : out STD_LOGIC;
sys_gpo0 : out unsigned(31 downto 0);
sys_gpo1 : out unsigned(31 downto 0);
sys_gpi0 : in unsigned(31 downto 0);
sys_gpi1 : in unsigned(31 downto 0)
);
END COMPONENT;
COMPONENT vga_frontend64
GENERIC
(
fifo_depth : integer;
fifo_almost_full_thresh : natural;
fifo_almost_empty_thresh : natural;
tsvga : vga_timespec_t
);
PORT
(
-- System signals
RST_I : in STD_LOGIC;
CLK_I : in STD_LOGIC;
-- JBUS Master signals
CYC_O : out STD_LOGIC;
STB_O : out STD_LOGIC;
WE_O : out STD_LOGIC;
SEL_O : out unsigned(7 downto 0);
ACK_I : in STD_LOGIC;
SRDY_I : in STD_LOGIC;
MRDY_O : out STD_LOGIC;
ADDR_O : out unsigned(31 downto 0);
MDAT_I : in unsigned(63 downto 0);
MDAT_O : out unsigned(63 downto 0);
-- JBUS Slave signals
INT_O : out STD_LOGIC;
CYC_I : in STD_LOGIC;
STB_I : in STD_LOGIC;
WE_I : in STD_LOGIC;
SEL_I : in unsigned(3 downto 0);
ACK_O : out STD_LOGIC;
SRDY_O : out STD_LOGIC;
MRDY_I : in STD_LOGIC;
ADDR_I : in unsigned(31 downto 0);
SDAT_I : in unsigned(31 downto 0);
SDAT_O : out unsigned(31 downto 0);
-- VGA signals
vga_clk_in : in std_logic;
vga_clk_ce : in std_logic;
vga_red : out unsigned(7 downto 0);
vga_green : out unsigned(7 downto 0);
vga_blue : out unsigned(7 downto 0);
vga_blank_n : out std_logic;
vga_sync_n : out std_logic;
vga_hsync : out std_logic;
vga_vsync : out std_logic
);
END COMPONENT;
signal cpu_clk : std_logic;
signal nmi : std_logic;
signal eb : std_logic;
signal sdram_clk0 : std_logic;
signal sdram_clk270 : std_logic;
signal sdram_clk270var : std_logic;
signal vga_clk : std_logic;
signal vga_ce : std_logic;
signal rst_in : std_logic;
signal int_timer : std_logic;
signal int_uart0 : std_logic;
signal int_uart1 : std_logic;
signal uart1_tx : std_logic;
signal uart1_rx : std_logic;
signal usb_addr : unsigned(3 downto 0);
signal ac97_rstn : std_logic;
signal mem_mapped_io : std_logic;
signal flash_rstn : std_logic;
signal flash_page_mode_en : std_logic;
signal flash_addr : unsigned(24 downto 0);
signal ps2_0_clk_rx : std_logic;
signal ps2_0_data_rx : std_logic;
signal ps2_0_clk_tx : std_logic;
signal ps2_0_data_tx : std_logic;
signal ps2_1_clk_rx : std_logic;
signal ps2_1_data_rx : std_logic;
signal ps2_1_clk_tx : std_logic;
signal ps2_1_data_tx : std_logic;
-- Arbiter
constant ARB_MAX_MASTER : natural := 2;
signal arb_idx : natural range 0 to ARB_MAX_MASTER-1;
signal arb_req : unsigned (ARB_MAX_MASTER-1 downto 0);
signal arb_gnt : unsigned (ARB_MAX_MASTER-1 downto 0);
-- J-Bus signals
signal CLK_O : std_logic;
signal RST_O : std_logic;
signal INT : unsigned(5 downto 0);
signal MDAT_I : word_t;
signal MDAT_O : unsigned(63 downto 0);
signal ADDR_O : word_t;
signal SEL_O : unsigned(7 downto 0);
signal WE_O : std_logic;
signal CYC_O : std_logic;
signal STB_O : std_logic;
signal ACK_I : std_logic;
signal SRDY_I : std_logic;
signal MRDY_O : std_logic;
-- CPU Master
signal MRDY_O_cpu : std_logic;
signal MDAT_O_cpu : word_t;
signal ADDR_O_cpu : word_t;
signal SEL_O_cpu : unsigned(3 downto 0);
signal WE_O_cpu : std_logic;
signal CYC_O_cpu : std_logic;
signal STB_O_cpu : std_logic;
signal SRDY_I_cpu : std_logic;
signal ACK_I_cpu : std_logic;
-- VGA Master
signal MRDY_O_vga : std_logic;
signal ADDR_O_vga : word_t;
signal SEL_O_vga : unsigned(7 downto 0);
signal WE_O_vga : std_logic;
signal CYC_O_vga : std_logic;
signal STB_O_vga : std_logic;
signal SRDY_I_vga : std_logic;
signal ACK_I_vga : std_logic;
signal MDAT_I_vga : unsigned(63 downto 0);
signal MDAT_O_vga : unsigned(63 downto 0);
-- Slaves
signal CYC_I_flash : std_logic;
signal ACK_O_flash : std_logic;
signal SRDY_O_flash : std_logic;
signal SDAT_O_flash : unsigned(31 downto 0);
signal CYC_I_usb : std_logic;
signal ACK_O_usb : std_logic;
signal SRDY_O_usb : std_logic;
signal SDAT_O_usb : unsigned(31 downto 0);
signal CYC_I_sdram : std_logic;
signal ACK_O_sdram : std_logic;
signal SRDY_O_sdram : std_logic;
signal SDAT_O_sdram : unsigned(63 downto 0);
signal CYC_I_rom : std_logic;
signal ACK_O_rom : std_logic;
signal SRDY_O_rom : std_logic;
signal SDAT_O_rom : unsigned(31 downto 0);
signal CYC_I_gpio : std_logic;
signal ACK_O_gpio : std_logic;
signal SRDY_O_gpio : std_logic;
signal SDAT_O_gpio : unsigned(31 downto 0);
signal CYC_I_uart0 : std_logic;
signal ACK_O_uart0 : std_logic;
signal SRDY_O_uart0 : std_logic;
signal SDAT_O_uart0 : unsigned(31 downto 0);
signal CYC_I_uart1 : std_logic;
signal ACK_O_uart1 : std_logic;
signal SRDY_O_uart1 : std_logic;
signal SDAT_O_uart1 : unsigned(31 downto 0);
signal INT_O_vga : std_logic;
signal CYC_I_vga : std_logic;
signal ACK_O_vga : std_logic;
signal SRDY_O_vga : std_logic;
signal SDAT_O_vga : unsigned(31 downto 0);
signal INT_O_ac97 : std_logic;
signal CYC_I_ac97 : std_logic;
signal ACK_O_ac97 : std_logic;
signal SRDY_O_ac97 : std_logic;
signal SDAT_O_ac97 : unsigned(31 downto 0);
signal INT_O_ps2_0 : std_logic;
signal CYC_I_ps2_0 : std_logic;
signal ACK_O_ps2_0 : std_logic;
signal SRDY_O_ps2_0 : std_logic;
signal SDAT_O_ps2_0 : unsigned(31 downto 0);
signal INT_O_ps2_1 : std_logic;
signal CYC_I_ps2_1 : std_logic;
signal ACK_O_ps2_1 : std_logic;
signal SRDY_O_ps2_1 : std_logic;
signal SDAT_O_ps2_1 : unsigned(31 downto 0);
signal gpo0 : unsigned(31 downto 0);
signal gpo1 : unsigned(31 downto 0);
signal gpi0 : unsigned(31 downto 0);
signal gpi1 : unsigned(31 downto 0);
signal debug : unsigned(1 downto 0);
-- DDR SDRAM
constant BURST_LEN : natural := 2;
constant vga_freq : real := real(tsvga.f_pxl_clk)/1.0E6;
-- attribute rom_style: string;
-- attribute rom_style of cmd_fifo_dout: signal is "DISTRIBUTED";
-- attribute rom_style of cpu_cpu_write_fifo_dout: signal is "DISTRIBUTED";
-- attribute rom_style of cpu_read_fifo_dout: signal is "DISTRIBUTED";
type mem_area_t is (mem_dead, mem_flash, mem_usb, mem_rom, mem_gpio, mem_uart0, mem_uart1, mem_ps2_0, mem_ps2_1, mem_sdram, mem_vga, mem_ac97);
signal mem_area : mem_area_t;
attribute KEEP : string;
attribute KEEP of vga_clk : signal is "TRUE";
attribute KEEP of sdram_clk0 : signal is "TRUE";
attribute KEEP of cpu_clk : signal is "TRUE";
attribute KEEP of CLK_O : signal is "TRUE";
attribute KEEP of RST_O : signal is "TRUE";
BEGIN
------------------------------------
-- GPO1 bits used for
-- 0 : USB reset
-- 1 : USB interrupt enable
-- 2 : AC97 interrupt enable
-- others : reserved
------------------------------------
eb <= sys_dip(7);
gpi0(4 downto 0) <= sys_btn;
gpi1(7 downto 0) <= sys_dip;
sys_led <= gpo0(8 downto 0);
sys_error <= debug;
nmi <= not sys_rst_n_in;
rst_in <= not sys_rst_n_in and sys_btn(0);
sys_usb_rstn <= not gpo1(0);
sys_flash_byten <= '1';
sys_usb_a <= usb_Addr(3 downto 2);
sys_flash_a <= '0' & flash_addr(24 downto 2) & '0';
flash_page_mode_en <= not mem_mapped_io;
sys_flash_ac97_rstn <= ac97_rstn and flash_rstn;
sys_uart1_tx <= uart1_tx;
sys_uart2_tx <= uart1_tx;
uart1_rx <= sys_uart1_rx and sys_uart2_rx;
sys_uart3_tx <= sys_uart3_rx;
sys_vga_clk <= vga_clk;
vga_ce <= not RST_O;
---------------------------------------------------------------
-- Arbiter
MRDY_O <= MRDY_O_cpu when arb_gnt(0) = '1' else MRDY_O_vga when arb_gnt(1) = '1' else '0';
MDAT_O <= (MDAT_O_cpu & MDAT_O_cpu) when arb_gnt(0) = '1' else MDAT_O_vga when arb_gnt(1) = '1' else (others => '0');
ADDR_O <= ADDR_O_cpu when arb_gnt(0) = '1' else ADDR_O_vga when arb_gnt(1) = '1' else (others => '0');
SEL_O <= ("0000" & SEL_O_cpu) when arb_gnt(0) = '1' else SEL_O_vga when arb_gnt(1) = '1' else (others => '0');
WE_O <= WE_O_cpu when arb_gnt(0) = '1' else WE_O_vga when arb_gnt(1) = '1' else '0';
CYC_O <= CYC_O_cpu when arb_gnt(0) = '1' else CYC_O_vga when arb_gnt(1) = '1' else '0';
STB_O <= STB_O_cpu when arb_gnt(0) = '1' else STB_O_vga when arb_gnt(1) = '1' else '0';
SRDY_I_cpu <= SRDY_I and arb_gnt(0);
SRDY_I_vga <= SRDY_I and arb_gnt(1);
ACK_I_cpu <= ACK_I and arb_gnt(0);
ACK_I_vga <= ACK_I and arb_gnt(1);
arb_req(0) <= CYC_O_cpu;
arb_req(1) <= CYC_O_vga;
MDAT_I_vga <= SDAT_O_sdram;
arbiter_proc:
process(CLK_O)
begin
if rising_edge(CLK_O) then
if RST_O = '1' then
arb_gnt <= (others => '0');
arb_idx <= 0;
elsif arb_req(arb_idx) = '0' then
if arb_idx /= ARB_MAX_MASTER-1 then
arb_idx <= arb_idx + 1;
else
arb_idx <= 0;
end if;
else
arb_gnt <= (others => '0');
arb_gnt(arb_idx) <= '1';
end if;
end if;
end process;
int_sample:
process(CLK_O)
begin
if rising_edge(CLK_O) then
INT <= int_timer & (INT_O_ps2_0 or INT_O_ps2_1) & (INT_O_vga or (gpo1(2) and INT_O_ac97)) & (gpo1(1) and sys_usb_int) & (int_uart0 or int_uart1) & sys_btn(4);
end if;
end process;
mem_mux:
process(ADDR_O)
begin
mem_area <= mem_dead;
mem_mapped_io <= '0';
if ADDR_O(31 downto 28) = X"0" then
mem_area <= mem_flash;
elsif ADDR_O(31 downto 28) = X"A" then
mem_mapped_io <= '1';
if ADDR_O(27 downto 26) = "00" then
if ADDR_O(18 downto 16) = "000" then
mem_area <= mem_gpio;
elsif ADDR_O(18 downto 16) = "001" then
if ADDR_O(9 downto 8) = "00" then
mem_area <= mem_uart0;
elsif ADDR_O(9 downto 8) = "01" then
mem_area <= mem_uart1;
elsif ADDR_O(9 downto 8) = "10" then
mem_area <= mem_ps2_0;
elsif ADDR_O(9 downto 8) = "11" then
mem_area <= mem_ps2_1;
end if;
elsif ADDR_O(18 downto 16) = "010" then
mem_area <= mem_usb;
elsif ADDR_O(18 downto 16) = "011" then
mem_area <= mem_vga;
elsif ADDR_O(18 downto 16) = "100" then
mem_area <= mem_ac97;
end if;
elsif ADDR_O(27 downto 26) = "01" then
mem_area <= mem_flash;
end if;
elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '0') then
mem_area <= mem_rom;
elsif (ADDR_O(31 downto 28) = X"8" or ADDR_O(30) = '1') then
mem_area <= mem_sdram;
end if;
end process;
signal_mux:
process(mem_area, CYC_O)
begin
CYC_I_uart0 <= '0';
CYC_I_uart1 <= '0';
CYC_I_ps2_0 <= '0';
CYC_I_ps2_1 <= '0';
CYC_I_gpio <= '0';
CYC_I_flash <= '0';
CYC_I_usb <= '0';
CYC_I_rom <= '0';
CYC_I_sdram <= '0';
CYC_I_vga <= '0';
CYC_I_ac97 <= '0';
case mem_area is
when mem_gpio =>
CYC_I_gpio <= CYC_O;
when mem_uart0 =>
CYC_I_uart0 <= CYC_O;
when mem_uart1 =>
CYC_I_uart1 <= CYC_O;
when mem_ps2_0 =>
CYC_I_ps2_0 <= CYC_O;
when mem_ps2_1 =>
CYC_I_ps2_1 <= CYC_O;
when mem_flash =>
CYC_I_flash <= CYC_O;
when mem_usb =>
CYC_I_usb <= CYC_O;
when mem_rom =>
CYC_I_rom <= CYC_O;
when mem_sdram =>
CYC_I_sdram <= CYC_O;
when mem_vga =>
CYC_I_vga <= CYC_O;
when mem_ac97 =>
CYC_I_ac97 <= CYC_O;
when others => null;
end case;
end process;
------------------------------------------------------------------
SRDY_I <= SRDY_O_flash or SRDY_O_usb or SRDY_O_sdram or SRDY_O_rom or SRDY_O_uart0 or SRDY_O_uart1 or SRDY_O_ps2_0 or SRDY_O_ps2_1 or SRDY_O_gpio or SRDY_O_vga or SRDY_O_ac97;
ACK_I <= ACK_O_flash or ACK_O_usb or ACK_O_sdram or ACK_O_rom or ACK_O_uart0 or ACK_O_uart1 or ACK_O_ps2_0 or ACK_O_ps2_1 or ACK_O_gpio or ACK_O_vga or ACK_O_ac97;
MDAT_I <= SDAT_O_sdram(31 downto 0) when CYC_I_sdram = '1' else
SDAT_O_rom when CYC_I_rom = '1' else
SDAT_O_flash when CYC_I_flash = '1' else
SDAT_O_usb when CYC_I_usb = '1' else
SDAT_O_uart0 when CYC_I_uart0 = '1' else
SDAT_O_uart1 when CYC_I_uart1 = '1' else
SDAT_O_ps2_0 when CYC_I_ps2_0 = '1' else
SDAT_O_ps2_1 when CYC_I_ps2_1 = '1' else
SDAT_O_vga when CYC_I_vga = '1' else
SDAT_O_ac97 when CYC_I_ac97 = '1' else
SDAT_O_gpio when CYC_I_gpio = '1' else X"DEADBEEF";
------------------------------------------------------------------
inst_mips_top: mips_top
PORT MAP
(
debug => debug,
eb => eb,
nmi => nmi,
cpu_clk => cpu_clk,
RST_I => RST_O,
CLK_I => CLK_O,
ACK_I => ACK_I_cpu,
SRDY_I => SRDY_I_cpu,
MRDY_O => MRDY_O_cpu,
CYC_O => CYC_O_cpu,
STB_O => STB_O_cpu,
WE_O => WE_O_cpu,
SEL_O => SEL_O_cpu,
DAT_I => MDAT_I,
DAT_O => MDAT_O_cpu,
ADDR_O => ADDR_O_cpu,
INT => INT
);
inst_rom_wb : rom_wb
PORT MAP
(
CLK_I => CLK_O,
RST_I => RST_O,
CYC_I => CYC_I_rom,
STB_I => STB_O,
ACK_O => ACK_O_rom,
MRDY_I => MRDY_O,
SRDY_O => SRDY_O_rom,
ADDR_I => ADDR_O,
DAT_O => SDAT_O_rom
);
inst_lcd_port: lcd_port
PORT MAP
(
clk => CLK_O,
rst => RST_O,
we => '0',
din => X"00",
dout => open,
lcd_d => sys_lcd_d,
lcd_e => sys_lcd_e,
lcd_rs => sys_lcd_rs,
lcd_rw => sys_lcd_rw
);
inst_gpio_wb : gpio_wb
GENERIC MAP
(
f_sysclk => sys_freq
)
PORT MAP
(
CLK_I => CLK_O,
RST_I => RST_O,
CYC_I => CYC_I_gpio,
STB_I => STB_O,
SEL_I => SEL_O(3 downto 0),
WE_I => WE_O,
ACK_O => ACK_O_gpio,
SRDY_O => SRDY_O_gpio,
MRDY_I => MRDY_O,
ADDR_I => ADDR_O,
DAT_I => MDAT_O(31 downto 0),
DAT_O => SDAT_O_gpio,
INT_TIM_O => int_timer,
sys_gpo0 => gpo0,
sys_gpo1 => gpo1,
sys_gpi0 => gpi0,
sys_gpi1 => gpi1
);
inst_flash_port : async_port_wb
GENERIC MAP
(
f_sysclk => sys_freq,
addr_width => 25,
data_width => 32,
byte_sel_width => 1,
async_timespec => ts_flash
)
PORT MAP
(
CLK_I => CLK_O,
RST_I => RST_O,
CYC_I => CYC_I_flash,
STB_I => STB_O,
WE_I => WE_O,
ACK_O => ACK_O_flash,
SRDY_O => SRDY_O_flash,
MRDY_I => MRDY_O,
SEL_I => SEL_O(3 downto 0),
ADDR_I => ADDR_O,
DAT_I => MDAT_O(31 downto 0),
DAT_O => SDAT_O_flash,
page_mode_en => flash_page_mode_en,
async_a => flash_addr,
async_d => sys_flash_d,
async_cs => sys_flash_ce,
async_wr => sys_flash_wrn,
async_rd => sys_flash_rdn,
async_be => open,
async_rst => flash_rstn
);
inst_usb_port : async_port_wb
GENERIC MAP
(
f_sysclk => sys_freq,
addr_width => 4,
data_width => 16,
byte_sel_width => 1,
async_timespec => ts_usb
)
PORT MAP
(
CLK_I => CLK_O,
RST_I => RST_O,
CYC_I => CYC_I_usb,
STB_I => STB_O,
WE_I => WE_O,
ACK_O => ACK_O_usb,
SRDY_O => SRDY_O_usb,
MRDY_I => MRDY_O,
SEL_I => SEL_O(3 downto 0),
ADDR_I => ADDR_O,
DAT_I => MDAT_O(31 downto 0),
DAT_O => SDAT_O_usb,
page_mode_en => '0',
async_a => usb_addr,
async_d => sys_usb_d,
async_cs => sys_usb_csn,
async_wr => sys_usb_wrn,
async_rd => sys_usb_rdn,
async_be => open,
async_rst => open
);
inst_uart_wb_0 : uart_wb
PORT MAP
(
CLK_I => CLK_O,
RST_I => RST_O,
CYC_I => CYC_I_uart0,
STB_I => STB_O,
SEL_I => SEL_O(3 downto 0),
WE_I => WE_O,
ACK_O => ACK_O_uart0,
SRDY_O => SRDY_O_uart0,
MRDY_I => MRDY_O,
ADDR_I => ADDR_O,
DAT_I => MDAT_O(31 downto 0),
DAT_O => SDAT_O_uart0,
INT_O => int_uart0,
ser_rx => sys_uart0_rx,
ser_tx => sys_uart0_tx
);
inst_uart_wb_1 : uart_wb
PORT MAP
(
CLK_I => CLK_O,
RST_I => RST_O,
CYC_I => CYC_I_uart1,
STB_I => STB_O,
SEL_I => SEL_O(3 downto 0),
WE_I => WE_O,
ACK_O => ACK_O_uart1,
SRDY_O => SRDY_O_uart1,
MRDY_I => MRDY_O,
ADDR_I => ADDR_O,
DAT_I => MDAT_O(31 downto 0),
DAT_O => SDAT_O_uart1,
INT_O => int_uart1,
ser_rx => uart1_rx,
ser_tx => uart1_tx
);
inst_clockgen : entity work.clockgen
GENERIC MAP
(
clk_in_freq => sys_freq_in,
sys_clk_out_freq => sys_freq,
vga_clk_out_freq => vga_freq,
sdr0_clk_out_phaseshift => 0,
sdr1_clk_out_phaseshift => 0
)
PORT MAP
(
-- Clocks and Reset
rst_in => rst_in, -- external async reset, low active
clk_in => sys_clk_in, -- system clock (e.g. 100MHz), from board
sys_rst_out => RST_O,
sys_clk_out => CLK_O,
vga_clk_out => vga_clk,
cpu_clk_out => cpu_clk,
sdr0_clk_fb_in => sys_sdr_clk_fb, -- feedback clock
sdr0_clk0_out => sdram_clk0, -- System clock #0, dcm#0 output 0�
sdr0_clk270_out => sdram_clk270, -- System clock #0, dcm#0 output 270�
sdr1_clk0_out => open, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0�
sdr1_clk270_out => sdram_clk270var -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270�
);
inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend64_wb
GENERIC MAP
(
BL => BURST_LEN,
f_sysclk => sys_freq,
f_sdrclk => sys_freq,
fifo_depth => 5
)
PORT MAP
(
RST_I => RST_O,
CLK_I => CLK_O,
SDRAM_CLK0_I => sdram_clk0,
SDRAM_CLK270_I => sdram_clk270,
SDRAM_CLK270VAR_I => sdram_clk270var,
CYC_I => CYC_I_sdram,
STB_I => STB_O,
SEL_I => SEL_O,
WE_I => WE_O,
ACK_O => ACK_O_sdram,
MRDY_I => MRDY_O,
SRDY_O => SRDY_O_sdram,
ADDR_I => ADDR_O,
DAT_I => MDAT_O,
DAT_O => SDAT_O_sdram,
-- SDRAM signals
sd_clk_p => sys_sdr_clk_p,
sd_clk_n => sys_sdr_clk_n,
sd_cke => sys_sdr_cke_q,
sd_cs_n => sys_sdr_cs_qn,
sd_cas_n => sys_sdr_cas_qn,
sd_ras_n => sys_sdr_ras_qn,
sd_we_n => sys_sdr_we_qn,
sd_addr => sys_sdr_a_q,
sd_ba => sys_sdr_ba_q,
sd_dm => sys_sdr_dm_q,
sd_dqs => sys_sdr_dqs_q,
sd_data => sys_sdr_data
);
inst_vga_frontend : vga_frontend64
GENERIC MAP
(
fifo_depth => 2048,
fifo_almost_full_thresh => 2048-128,
fifo_almost_empty_thresh => 256,
tsvga => tsvga
)
PORT MAP
(
-- System signals
RST_I => RST_O,
CLK_I => CLK_O,
-- JBUS Master signals
CYC_O => CYC_O_vga,
STB_O => STB_O_vga,
WE_O => WE_O_vga,
SEL_O => SEL_O_vga,
ACK_I => ACK_I_vga,
SRDY_I => SRDY_I_vga,
MRDY_O => MRDY_O_vga,
ADDR_O => ADDR_O_vga,
MDAT_I => MDAT_I_vga,
MDAT_O => MDAT_O_vga,
-- JBUS Slave signals
INT_O => INT_O_vga,
CYC_I => CYC_I_vga,
STB_I => STB_O,
WE_I => WE_O,
SEL_I => SEL_O(3 downto 0),
ACK_O => ACK_O_vga,
SRDY_O => SRDY_O_vga,
MRDY_I => MRDY_O,
ADDR_I => ADDR_O,
SDAT_I => MDAT_O(31 downto 0),
SDAT_O => SDAT_O_vga,
-- VGA signals
vga_clk_in => vga_clk,
vga_clk_ce => vga_ce,
vga_red => sys_vga_red,
vga_green => sys_vga_green,
vga_blue => sys_vga_blue,
vga_blank_n => sys_vga_blank_n,
vga_sync_n => sys_vga_sync_n,
vga_hsync => sys_vga_hsync,
vga_vsync => sys_vga_vsync
);
inst_ac97_wb : entity work.ac97_wb
GENERIC MAP
(
fifo_depth => 8
)
PORT MAP
(
-- J-Bus domain
CLK_I => CLK_O,
RST_I => RST_O,
CYC_I => CYC_I_ac97,
STB_I => STB_O,
WE_I => WE_O,
ACK_O => ACK_O_ac97,
SRDY_O => SRDY_O_ac97,
MRDY_I => MRDY_O,
ADDR_I => ADDR_O,
DAT_I => MDAT_O(31 downto 0),
DAT_O => SDAT_O_ac97,
INT_O => INT_O_ac97,
-- AC97 domain
ac97_sdata_in => sys_ac97_sdata_in,
ac97_bit_clk => sys_ac97_bit_clk,
ac97_reset_n => ac97_rstn,
ac97_sdata_out => sys_ac97_sdata_out,
ac97_ssync => sys_ac97_ssync
);
inst_ps2_wb_0: entity work.ps2_wb
GENERIC MAP
(
f_sys_clk => sys_freq
)
PORT MAP
(
CLK_I => CLK_O,
RST_I => RST_O,
CYC_I => CYC_I_ps2_0,
STB_I => STB_O,
SEL_I => SEL_O(3 downto 0),
WE_I => WE_O,
ACK_O => ACK_O_ps2_0,
SRDY_O => SRDY_O_ps2_0,
MRDY_I => MRDY_O,
ADDR_I => ADDR_O,
DAT_I => MDAT_O(31 downto 0),
DAT_O => SDAT_O_ps2_0,
INT_O => INT_O_ps2_0,
clk_rx => ps2_0_clk_rx,
data_rx => ps2_0_data_rx,
clk_tx => ps2_0_clk_tx,
data_tx => ps2_0_data_tx
);
inst_ps2_phy_0: entity work.ps2_phy
PORT MAP
(
rst => RST_O,
clk => CLK_O,
ps2_clk => sys_ps2_0_clk,
ps2_data => sys_ps2_0_data,
rx_clk => ps2_0_clk_rx,
rx_data => ps2_0_data_rx,
tx_clk => ps2_0_clk_tx,
tx_data => ps2_0_data_tx
);
inst_ps2_wb_1: entity work.ps2_wb
GENERIC MAP
(
f_sys_clk => sys_freq
)
PORT MAP
(
CLK_I => CLK_O,
RST_I => RST_O,
CYC_I => CYC_I_ps2_1,
STB_I => STB_O,
SEL_I => SEL_O(3 downto 0),
WE_I => WE_O,
ACK_O => ACK_O_ps2_1,
SRDY_O => SRDY_O_ps2_1,
MRDY_I => MRDY_O,
ADDR_I => ADDR_O,
DAT_I => MDAT_O(31 downto 0),
DAT_O => SDAT_O_ps2_1,
INT_O => INT_O_ps2_1,
clk_rx => ps2_1_clk_rx,
data_rx => ps2_1_data_rx,
clk_tx => ps2_1_clk_tx,
data_tx => ps2_1_data_tx
);
inst_ps2_phy_1: entity work.ps2_phy
PORT MAP
(
rst => RST_O,
clk => CLK_O,
ps2_clk => sys_ps2_1_clk,
ps2_data => sys_ps2_1_data,
rx_clk => ps2_1_clk_rx,
rx_data => ps2_1_data_rx,
tx_clk => ps2_1_clk_tx,
tx_data => ps2_1_data_tx
);
------------------------------------------------------------------
END;
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