jens
eed1090f2d
git-svn-id: http://moon:8086/svn/vhdl/trunk@1427 cc03376c-175c-47c8-b038-4cd826a8556b
70 lines
1.5 KiB
VHDL
70 lines
1.5 KiB
VHDL
--------------------------------------------------------------------------------
|
|
-- Company:
|
|
-- Engineer:
|
|
--
|
|
-- Create Date: 21:44:36 09/24/05
|
|
-- Design Name:
|
|
-- Module Name: test_comp - Behavioral
|
|
-- Project Name:
|
|
-- Target Device:
|
|
-- Tool versions:
|
|
-- Description:
|
|
--
|
|
-- Dependencies:
|
|
--
|
|
-- Revision:
|
|
-- Revision 0.01 - File Created
|
|
-- Additional Comments:
|
|
--
|
|
--------------------------------------------------------------------------------
|
|
library IEEE;
|
|
use IEEE.STD_LOGIC_1164.ALL;
|
|
use IEEE.STD_LOGIC_ARITH.ALL;
|
|
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
|
|
|
---- Uncomment the following library declaration if instantiating
|
|
---- any Xilinx primitives in this code.
|
|
--library UNISIM;
|
|
--use UNISIM.VComponents.all;
|
|
|
|
entity test_comp is
|
|
Port ( clk : in std_logic;
|
|
rst : in std_logic;
|
|
led : out std_logic_vector(0 to 4);
|
|
btn : in std_logic_vector(0 to 4));
|
|
end test_comp;
|
|
|
|
architecture Behavioral of test_comp is
|
|
|
|
begin
|
|
|
|
-- Reset logic
|
|
reset_action: process(rst, clk, btn)
|
|
begin
|
|
if clk'event and clk = '1' then
|
|
if (rst = '0') then
|
|
led(0 to 4) <= (0 to 4 => '0');
|
|
else
|
|
if btn(0) = '1' then
|
|
led(0) <= '1';
|
|
end if;
|
|
if btn(1) = '1' then
|
|
led(1) <= '1';
|
|
end if;
|
|
if btn(2) = '1' then
|
|
led(2) <= '1';
|
|
end if;
|
|
if btn(3) = '1' then
|
|
led(3) <= '1';
|
|
end if;
|
|
if btn(4) = '1' then
|
|
led(4) <= '1';
|
|
end if;
|
|
-- led <= btn;
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
|
|
end Behavioral;
|