jens
228e893904
git-svn-id: http://moon:8086/svn/vhdl/trunk@1111 cc03376c-175c-47c8-b038-4cd826a8556b
72 lines
2.3 KiB
VHDL
72 lines
2.3 KiB
VHDL
-------------------------------------------------------------------------
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-- Project: Dual-Port RAM with 1 clock latency for simulation
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-- This file: Dual-Port RAM 1 write, 1 read, 2 clocks, registered address
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-- Copyright (C) 2007 J. Ahrensfeld
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-- This library is free software; you can redistribute it and/or
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-- modify it under the terms of the GNU Lesser General Public
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-- License as published by the Free Software Foundation; either
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-- version 2.1 of the License, or (at your option) any later version.
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-- This library is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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-- Lesser General Public License for more details.
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-- You should have received a copy of the GNU Lesser General Public
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-- License along with this library; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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-- For questions and ideas, please contact the author at jens@jayfield.org
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-----------------------------------------------------------------------
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-- $Header: D:\usr\cvsroot/VHDL/lib/rams/dpram_1w1r2c_ra_sim.vhd,v 1.1 2013/02/09 09:27:21 jens Exp $
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-----------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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entity dpram_1w1r1c_ra is
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Generic
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(
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addr_width : integer := 3;
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data_width : integer := 8
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);
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Port
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(
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clk : in STD_LOGIC;
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we_a : in STD_LOGIC;
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re_b : in STD_LOGIC;
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addr_a : in unsigned (addr_width-1 downto 0);
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addr_b : in unsigned (addr_width-1 downto 0);
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din_a : in unsigned (data_width-1 downto 0);
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dout_b : out unsigned (data_width-1 downto 0)
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);
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end dpram_1w1r1c_ra;
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architecture Behavioral of dpram_1w1r1c_ra is
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TYPE MEM IS ARRAY(0 TO 2**addr_width-1) OF unsigned(data_width-1 DOWNTO 0);
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SIGNAL ram_block: MEM;
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BEGIN
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PROCESS (clk)
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BEGIN
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IF (clk'event AND clk = '1') THEN
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IF (we_a = '1') THEN
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ram_block(to_integer(addr_a)) <= din_a;
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END IF;
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IF (re_b = '1') THEN
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dout_b <= ram_block(to_integer(addr_b));
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END IF;
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-- VHDL semantics imply that q doesn't get data
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-- in this clock cycle
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END IF;
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END PROCESS;
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end Behavioral;
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