jens
0d10a1c1c6
Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@938 cc03376c-175c-47c8-b038-4cd826a8556b
42 lines
837 B
VHDL
42 lines
837 B
VHDL
library IEEE;
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use IEEE.Std_Logic_1164.all;
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entity wire_delay is
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generic(a_to_b_loss : time := 1 ns;
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b_to_a_loss : time := 2 ns);
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port
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(A : inout Std_Logic;
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B : inout Std_Logic
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);
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end wire_delay;
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architecture behave of wire_delay is
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begin
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ABC0_Lbl: process
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variable ThenTime_v : time := 0 ns;
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function max(t1,t2 : time) return time is
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begin
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if (t1 > t2) then
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return t1;
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else
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return t2;
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end if;
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end;
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begin
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wait on A'transaction, B'transaction
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until ThenTime_v + max(a_to_b_loss, b_to_a_loss) < now;
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-- Break
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ThenTime_v := now;
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A <= 'Z';
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B <= 'Z';
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wait for 0 ns;
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-- Make
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A <= transport B after b_to_a_loss;
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B <= transport A after a_to_b_loss;
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end process ABC0_Lbl;
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end behave; |