jens
70e48af3ab
git-svn-id: http://moon:8086/svn/vhdl/trunk@1036 cc03376c-175c-47c8-b038-4cd826a8556b
156 lines
2.9 KiB
VHDL
156 lines
2.9 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 21:52:19 10/22/05
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-- Design Name:
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-- Module Name: singleshot - Behavioral
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-- Project Name:
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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-----------------------------------------------------------------------
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-- $Header: D:\usr\cvsroot/VHDL/lib/misc/singleshot.vhd,v 1.1 2008/08/23 08:20:29 Jens Exp $
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-----------------------------------------------------------------------
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-- Component Template
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--
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-- COMPONENT singleshot
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-- GENERIC (mode : integer);
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-- PORT(
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-- rst : IN std_logic;
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-- clk : IN std_logic;
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-- input : IN std_logic;
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-- output : OUT std_logic
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-- );
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-- END COMPONENT;
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--
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-- Instantation Template
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--
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-- singleshot_int: oneshot
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-- GENERIC MAP (
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-- mode => 1)
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-- PORT MAP(
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-- rst => ,
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-- clk => ,
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-- input => ,
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-- output =>
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-- );
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--
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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entity singleshot is
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Generic ( mode : integer range 0 to 2 := 1);
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Port ( rst : in std_logic;
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clk : in std_logic;
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input : in std_logic;
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output : out std_logic);
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end singleshot;
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architecture Behavioral of singleshot is
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type s_t is (idle, shot_in, active, shot_out);
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signal s, sn : s_t;
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begin
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process (rst, clk, sn)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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s <= idle;
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else
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s <= sn;
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end if;
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end if;
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end process;
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mode_1:
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if mode = 1 generate
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begin
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process (input, s)
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begin
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output <= '0';
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sn <= s;
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case s is
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when idle =>
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if input = '1' then
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sn <= shot_in;
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end if;
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when shot_in =>
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output <= '1';
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sn <= active;
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when active =>
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if input = '0' then
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sn <= shot_out;
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end if;
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when shot_out =>
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sn <= idle;
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when others => null;
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end case;
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end process;
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end generate;
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mode_0:
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if mode = 0 generate
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begin
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process (input, s)
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begin
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output <= '0';
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sn <= s;
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case s is
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when idle =>
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if input = '1' then
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sn <= shot_in;
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end if;
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when shot_in =>
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sn <= active;
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when active =>
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if input = '0' then
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sn <= shot_out;
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end if;
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when shot_out =>
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output <= '1';
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sn <= idle;
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when others => null;
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end case;
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end process;
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end generate;
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mode_2:
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if mode = 2 generate
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begin
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process (input, s)
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begin
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output <= '0';
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sn <= s;
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case s is
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when idle =>
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if input = '1' then
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sn <= shot_in;
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end if;
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when shot_in =>
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output <= '1';
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sn <= active;
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when active =>
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if input = '0' then
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sn <= shot_out;
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end if;
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when shot_out =>
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output <= '1';
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sn <= idle;
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when others => null;
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end case;
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end process;
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end generate;
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end Behavioral;
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