jens
bdb8fec295
git-svn-id: http://moon:8086/svn/vhdl/trunk@1424 cc03376c-175c-47c8-b038-4cd826a8556b
29 lines
1.6 KiB
Plaintext
29 lines
1.6 KiB
Plaintext
work "E:\work\lib\HDL\Cores\CPUs\DLX\dlx_types.vhdl"
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work "E:\work\lib\HDL\Cores\CPUs\DLX\dlx_instr.vhdl"
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work "E:\work\lib\HDL\Cores\CPUs\DLX\alu_types.vhdl"
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work "E:\work\lib\HDL\Cores\CPUs\DLX\reg_multiple_plus_one_out_reset.vhdl"
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work "E:\work\lib\HDL\Cores\CPUs\DLX\reg_multiple_plus_one_out.vhdl"
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work "E:\work\lib\HDL\Cores\CPUs\DLX\reg_multiple_out.vhdl"
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work "E:\work\lib\HDL\Cores\CPUs\DLX\reg_file.vhdl"
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work "E:\work\lib\HDL\Cores\CPUs\DLX\reg.vhdl"
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work "E:\work\lib\HDL\Cores\CPUs\DLX\mux2.vhdl"
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work "E:\work\lib\HDL\Cores\CPUs\DLX\ir_extender.vhdl"
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work "E:\work\lib\HDL\Cores\CPUs\DLX\controller.vhdl"
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work "E:\work\lib\HDL\Cores\CPUs\DLX\alu.vhdl"
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work "E:\work\lib\HDL\Cores\CPUs\DLX\reg_multiple_plus_one_out_reset-behavior.vhdl"
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work "E:\work\lib\HDL\Cores\CPUs\DLX\reg_multiple_plus_one_out-behavior.vhdl"
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work "E:\work\lib\HDL\Cores\CPUs\DLX\reg_multiple_out-behavior.vhdl"
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work "E:\work\lib\HDL\Cores\CPUs\DLX\reg_file-behavior.vhdl"
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work "E:\work\lib\HDL\Cores\CPUs\DLX\reg-behavior.vhdl"
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work "E:\work\lib\HDL\Cores\CPUs\DLX\mux2-behavior.vhdl"
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work "E:\work\lib\HDL\Cores\CPUs\DLX\ir_extender-behavior.vhdl"
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work "E:\work\lib\HDL\Cores\CPUs\DLX\controller-behavior.vhdl"
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work "E:\work\lib\HDL\Cores\CPUs\DLX\alu-behavior.vhdl"
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work "E:\work\lib\HDL\Cores\CPUs\DLX\memory.vhdl"
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work "E:\work\lib\HDL\Cores\CPUs\DLX\dlx.vhdl"
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work "E:\work\lib\HDL\Cores\CPUs\DLX\clock_gen.vhdl"
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work "E:\work\lib\HDL\Cores\CPUs\DLX\memory-file_loaded.vhdl"
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work "E:\work\lib\HDL\Cores\CPUs\DLX\dlx-rtl.vhdl"
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work "E:\work\lib\HDL\Cores\CPUs\DLX\clock_gen-behavior.vhdl"
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work "E:\work\lib\HDL\Cores\CPUs\DLX\dlx_test-verifier.vhdl"
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