112 lines
2.0 KiB
VHDL
112 lines
2.0 KiB
VHDL
-------------------------------------------------------------------------
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-- Project: SDRAM controller
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-- This file: Reset generator (Virtex-4 specific)
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--
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-- Copyright (C) 2007 J. Ahrensfeld
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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-- For questions and ideas, please contact the author at jens@jayfield.org
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--
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--------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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Library UNISIM;
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use UNISIM.vcomponents.all;
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entity reset is
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port
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(
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clk : in std_logic;
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rst_in : in std_logic;
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rst_out : out std_logic
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);
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end;
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architecture tech of reset is
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signal rst : std_logic;
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signal shift_pipe : std_logic_vector(3 downto 0);
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attribute KEEP : string;
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attribute KEEP of shift_pipe : signal is "TRUE";
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begin
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rst <= shift_pipe(0);
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bufg_reset: bufg
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port map
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(
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o => rst_out,
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i => rst
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);
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fdp0: fdp
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generic map
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(
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init => '1'
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)
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port map
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(
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d => rst_in,
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c => clk,
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pre => '0',
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q => shift_pipe(3)
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);
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fdp1: fdp
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generic map
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(
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init => '1'
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)
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port map
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(
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d => shift_pipe(3),
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c => clk,
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pre => '0',
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q => shift_pipe(2)
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);
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fdp2: fdp
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generic map
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(
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init => '1'
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)
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port map
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(
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d => shift_pipe(2),
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c => clk,
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pre => '0',
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q => shift_pipe(1)
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);
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fdp3: fdp
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generic map
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(
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init => '1'
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)
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port map
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(
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d => shift_pipe(1),
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c => clk,
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pre => '0',
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q => shift_pipe(0)
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);
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end tech;
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