jens
d0c4a3d800
git-svn-id: http://moon:8086/svn/vhdl/trunk@1425 cc03376c-175c-47c8-b038-4cd826a8556b
26 lines
594 B
C
26 lines
594 B
C
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//
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// CLOCK DIVIDER
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//
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// UNcomment the below to use a
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// clock divider. This will allow a much
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// faster external clock to be used and still
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// slow down the internal core frequency.
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// USE the paramter N in PC.V to adjust the
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// frequency. Minimum N is 3.
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// COMMNET the below to use the external clock
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// directly as is. Note that the core will
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// always run at 1/4 the external clock.
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//
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//`define use_clock_divider
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//
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// DEBUG SIGNALS
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//
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// UNcomment the below to activate the
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// test bus for observability during debug
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//
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// `define show_debug_pins
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