jens
e27c0f791a
Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@782 cc03376c-175c-47c8-b038-4cd826a8556b
5228 lines
395 KiB
Plaintext
5228 lines
395 KiB
Plaintext
Release 10.1.03 - xst K.39 (nt)
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Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
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--> Parameter TMPDIR set to W:/vhdl/projects/mips_sys/ise101/mips_sys/xst/projnav.tmp
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.13 secs
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--> Parameter xsthdpdir set to W:/vhdl/projects/mips_sys/ise101/mips_sys/xst
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.13 secs
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--> Reading design: mips_sys.prj
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TABLE OF CONTENTS
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1) Synthesis Options Summary
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2) HDL Compilation
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3) Design Hierarchy Analysis
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4) HDL Analysis
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5) HDL Synthesis
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5.1) HDL Synthesis Report
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6) Advanced HDL Synthesis
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6.1) Advanced HDL Synthesis Report
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7) Low Level Synthesis
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8) Partition Report
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9) Final Report
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9.1) Device utilization summary
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9.2) Partition Resource Summary
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9.3) TIMING REPORT
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=========================================================================
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* Synthesis Options Summary *
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=========================================================================
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---- Source Parameters
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Input File Name : "mips_sys.prj"
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Input Format : mixed
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Ignore Synthesis Constraint File : NO
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---- Target Parameters
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Output File Name : "mips_sys"
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Output Format : NGC
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Target Device : xc4vsx35-10-ff668
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---- Source Options
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Top Module Name : mips_sys
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Automatic FSM Extraction : YES
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FSM Encoding Algorithm : Auto
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Safe Implementation : No
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FSM Style : lut
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RAM Extraction : Yes
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RAM Style : Auto
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ROM Extraction : Yes
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Mux Style : Auto
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Decoder Extraction : YES
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Priority Encoder Extraction : YES
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Shift Register Extraction : YES
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Logical Shifter Extraction : YES
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XOR Collapsing : YES
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ROM Style : Auto
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Mux Extraction : YES
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Resource Sharing : NO
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Asynchronous To Synchronous : NO
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Use DSP Block : auto
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Automatic Register Balancing : Yes
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---- Target Options
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Add IO Buffers : YES
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Global Maximum Fanout : 500
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Add Generic Clock Buffer(BUFG) : 32
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Number of Regional Clock Buffers : 24
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Register Duplication : YES
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Move First FlipFlop Stage : YES
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Move Last FlipFlop Stage : YES
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Slice Packing : YES
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Optimize Instantiated Primitives : NO
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Use Clock Enable : Auto
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Use Synchronous Set : Auto
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Use Synchronous Reset : Auto
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Pack IO Registers into IOBs : true
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Equivalent register Removal : YES
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---- General Options
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Optimization Goal : Speed
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Optimization Effort : 1
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Power Reduction : NO
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Library Search Order : mips_sys.lso
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Keep Hierarchy : NO
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Netlist Hierarchy : as_optimized
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RTL Output : Yes
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Global Optimization : AllClockNets
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Read Cores : YES
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Write Timing Constraints : NO
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Cross Clock Analysis : NO
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Hierarchy Separator : /
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Bus Delimiter : <>
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Case Specifier : maintain
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Slice Utilization Ratio : 100
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BRAM Utilization Ratio : 100
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DSP48 Utilization Ratio : 100
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Verilog 2001 : YES
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Auto BRAM Packing : NO
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Slice Utilization Ratio Delta : 5
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=========================================================================
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=========================================================================
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* HDL Compilation *
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=========================================================================
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Compiling vhdl file "W:/vhdl/lib/FIFO/src/fifo_ctrl_pkg.vhd" in Library work.
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Architecture fifo_ctrl_pkg of Entity fifo_ctrl_pkg is up to date.
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Compiling vhdl file "W:/vhdl/lib/VGA_ctrl/src/vga_types.vhd" in Library work.
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Architecture vga_types of Entity vga_types is up to date.
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Compiling vhdl file "W:/vhdl/projects/mips_sys/src/sdram_config.vhd" in Library work.
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Compiling vhdl file "W:/vhdl/lib/FIFO/src/gray_counter.vhd" in Library work.
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Architecture behavioral of Entity gray_counter is up to date.
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Compiling vhdl file "W:/vhdl/lib/misc/singleshot.vhd" in Library work.
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Architecture behavioral of Entity singleshot is up to date.
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Compiling vhdl file "W:/vhdl/lib/VGA_ctrl/src/vga_sync.vhd" in Library work.
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Architecture behavioral of Entity vga_sync is up to date.
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Compiling vhdl file "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd" in Library work.
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Architecture sdram_types of Entity sdram_types is up to date.
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Compiling vhdl file "W:/vhdl/lib/FIFO/src/fifo_async_ctrl.vhd" in Library work.
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Architecture behavioral of Entity fifo_async_ctrl is up to date.
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Compiling vhdl file "W:/vhdl/lib/misc/dpram_1w1r.vhd" in Library work.
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Architecture behavioral of Entity dpram_1w1r is up to date.
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Compiling vhdl file "W:/vhdl/lib/misc/utils_pkg.vhd" in Library work.
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WARNING:HDLParsers:3534 - "W:/vhdl/lib/misc/utils_pkg.vhd" Line 155. In the function f_correct, not all control paths contain a return statement.
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Architecture utils_pkg of Entity utils_pkg is up to date.
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Compiling vhdl file "W:/vhdl/lib/ac97_ctrl/src/core/ac_in.vhd" in Library work.
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Architecture behavioral of Entity ac_in is up to date.
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Compiling vhdl file "W:/vhdl/lib/ac97_ctrl/src/core/ac_out.vhd" in Library work.
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Architecture behavioral of Entity ac_out is up to date.
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Compiling vhdl file "W:/vhdl/lib/FIFO/src/fifo_sync_ctrl.vhd" in Library work.
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Architecture behavioral of Entity fifo_sync_ctrl is up to date.
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Compiling vhdl file "W:/vhdl/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x16.vhd" in Library work.
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Architecture rtl of Entity char_rom is up to date.
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Compiling vhdl file "W:/vhdl/lib/VGA_ctrl/src/vga_timing.vhd" in Library work.
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Architecture behavioral of Entity vga_timing is up to date.
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Compiling vhdl file "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd" in Library work.
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Architecture behaviour of Entity sdram_ctrl is up to date.
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Compiling vhdl file "W:/vhdl/lib/FIFO/src/fifo_async.vhd" in Library work.
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Architecture behavioral of Entity fifo_async is up to date.
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Compiling vhdl file "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd" in Library work.
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Architecture behaviour of Entity sdram_cmd is up to date.
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Compiling vhdl file "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd" in Library work.
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Architecture tech of Entity ddr_phy is up to date.
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Compiling vhdl file "W:/vhdl/lib/uart/kcuart_rx.vhd" in Library work.
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Architecture low_level_definition of Entity kcuart_rx is up to date.
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Compiling vhdl file "W:/vhdl/lib/uart/bbfifo_16x8.vhd" in Library work.
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Architecture low_level_definition of Entity bbfifo_16x8 is up to date.
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Compiling vhdl file "W:/vhdl/lib/uart/kcuart_tx.vhd" in Library work.
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Architecture low_level_definition of Entity kcuart_tx is up to date.
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Compiling vhdl file "W:/vhdl/lib/ps2_port/src/debounce.vhd" in Library work.
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Architecture behavioral of Entity debounce is up to date.
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Compiling vhdl file "W:/vhdl/lib/ps2_port/src/ps2_core.vhd" in Library work.
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Architecture behavioral of Entity ps2_core is up to date.
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Compiling vhdl file "W:/vhdl/lib/FIFO/src/fifo_sync.vhd" in Library work.
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Architecture behavioral of Entity fifo_sync is up to date.
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Compiling vhdl file "W:/vhdl/lib/ac97_ctrl/src/core/ac_io.vhd" in Library work.
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Architecture behavioral of Entity ac_io is up to date.
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Compiling vhdl file "W:/vhdl/lib/VGA_ctrl/src/vga_backend.vhd" in Library work.
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Architecture behavioral of Entity vga_backend is up to date.
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Compiling vhdl file "W:/vhdl/lib/VGA_ctrl/src/char_gen.vhd" in Library work.
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Architecture behavioral of Entity char_gen is up to date.
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Compiling vhdl file "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd" in Library work.
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Architecture rtl of Entity sdram_ctrl_top is up to date.
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Compiling vhdl file "W:/vhdl/lib/uart/uart_tx.vhd" in Library work.
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Architecture macro_level_definition of Entity uart_tx is up to date.
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Compiling vhdl file "W:/vhdl/lib/uart/uart_rx.vhd" in Library work.
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Architecture macro_level_definition of Entity uart_rx is up to date.
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Compiling vhdl file "W:/vhdl/lib/misc/async_types.vhd" in Library work.
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Architecture async_types of Entity async_types is up to date.
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Compiling vhdl file "W:/vhdl/projects/mips_sys/src/bootloader.ROM_ld.vhd" in Library work.
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Architecture data of Entity rom is up to date.
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Compiling vhdl file "W:/vhdl/lib/CPUs/MIPS/src/core/mips_types.vhd" in Library work.
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Architecture mips_types of Entity mips_types is up to date.
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Compiling vhdl file "W:/vhdl/projects/mips_sys/src/async_defs.vhd" in Library work.
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Compiling vhdl file "W:/vhdl/lib/misc/rom_wb.vhd" in Library work.
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Architecture behavior of Entity rom_wb is up to date.
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Compiling vhdl file "W:/vhdl/lib/misc/lcd_port.vhd" in Library work.
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Architecture behavioral of Entity lcd_port is up to date.
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Compiling vhdl file "W:/vhdl/lib/misc/gpio_wb.vhd" in Library work.
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Architecture behavior of Entity gpio_wb is up to date.
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Compiling vhdl file "W:/vhdl/lib/misc/async_port_wb.vhd" in Library work.
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Architecture behavioral of Entity async_port_wb is up to date.
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Compiling vhdl file "W:/vhdl/lib/uart/uart_wb.vhd" in Library work.
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Architecture behavior of Entity uart_wb is up to date.
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Compiling vhdl file "W:/vhdl/projects/mips_sys/src/clockgen_virtex4.vhd" in Library work.
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Architecture tech of Entity clockgen is up to date.
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Compiling vhdl file "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd" in Library work.
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Architecture struct of Entity sdram_ctrl_frontend64_wb is up to date.
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Compiling vhdl file "W:/vhdl/lib/VGA_ctrl/src/vga_frontend64.vhd" in Library work.
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Architecture behavioral of Entity vga_frontend64 is up to date.
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Compiling vhdl file "W:/vhdl/lib/ac97_ctrl/src/core/ac97_wb.vhd" in Library work.
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Architecture behavior of Entity ac97_wb is up to date.
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Compiling vhdl file "W:/vhdl/lib/ps2_port/src/ps2_wb.vhd" in Library work.
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Architecture behavior of Entity ps2_wb is up to date.
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Compiling vhdl file "W:/vhdl/lib/ps2_port/src/ps2_phy_virtex.vhd" in Library work.
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Architecture behavioral of Entity ps2_phy is up to date.
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Compiling vhdl file "W:/vhdl/projects/mips_sys/src/mips_sys.vhd" in Library work.
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Architecture behavior of Entity mips_sys is up to date.
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=========================================================================
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* Design Hierarchy Analysis *
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=========================================================================
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Analyzing hierarchy for entity <mips_sys> in library <work> (architecture <behavior>) with generics.
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sdram_phaseshift = 0
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sys_freq = 100.000000
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sys_freq_in = 100.000000
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tsvga = (f_pxl_clk => 40000000
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nfps => 60
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ts_h => (ncyc_scan => 800
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ncyc_porch_front => 40
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ncyc_sync_pulse => 128
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ncyc_porch_back => 88
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sync_polarity => '0')
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ts_v => (ncyc_scan => 600
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ncyc_porch_front => 1
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ncyc_sync_pulse => 4
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ncyc_porch_back => 23
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sync_polarity => '0'))
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Analyzing hierarchy for entity <rom_wb> in library <work> (architecture <behavior>).
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Analyzing hierarchy for entity <lcd_port> in library <work> (architecture <behavioral>).
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Analyzing hierarchy for entity <gpio_wb> in library <work> (architecture <behavior>) with generics.
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f_sysclk = 100.000000
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Analyzing hierarchy for entity <async_port_wb> in library <work> (architecture <behavioral>) with generics.
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addr_width = 25
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async_timespec = (T_leadin => 0.000000
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T_pulse_rd => 120.000000
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T_pulse_wr => 70.000000
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T_leadout => 0.000000
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T_release => 40.000000
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T_pulse_rst => 80.000000
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T_pulse_page_rd => 30.000000
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can_page_rd => true
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nbits_page_rd => 4
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pol_cs => '1'
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pol_oe => '0'
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pol_we => '0'
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pol_be => '0'
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pol_rst => '0')
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byte_sel_width = 1
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data_width = 32
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f_sysclk = 100.000000
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Analyzing hierarchy for entity <async_port_wb> in library <work> (architecture <behavioral>) with generics.
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addr_width = 4
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async_timespec = (T_leadin => 10.000000
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T_pulse_rd => 60.000000
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T_pulse_wr => 60.000000
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T_leadout => 10.000000
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T_release => 80.000000
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T_pulse_rst => 80.000000
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T_pulse_page_rd => 0.000000
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can_page_rd => false
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nbits_page_rd => 0
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pol_cs => '0'
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pol_oe => '0'
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pol_we => '0'
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pol_be => '0'
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pol_rst => '0')
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byte_sel_width = 1
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data_width = 16
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f_sysclk = 100.000000
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Analyzing hierarchy for entity <uart_wb> in library <work> (architecture <behavior>) with generics.
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simulate_tx = false
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Analyzing hierarchy for entity <clockgen> in library <work> (architecture <tech>) with generics.
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clk_in_freq = 100.000000
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sdr0_clk_out_phaseshift = 0
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sdr1_clk_out_phaseshift = 0
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sys_clk_out_freq = 100.000000
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vga_clk_out_freq = 40.000000
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WARNING:Xst:1748 - "W:/vhdl/lib/misc/utils_pkg.vhd" line 131: VHDL Assertion Statement with non constant condition is ignored.
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WARNING:Xst:1748 - "W:/vhdl/lib/misc/utils_pkg.vhd" line 103: VHDL Assertion Statement with non constant condition is ignored.
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WARNING:Xst:1748 - "W:/vhdl/lib/misc/utils_pkg.vhd" line 131: VHDL Assertion Statement with non constant condition is ignored.
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WARNING:Xst:1748 - "W:/vhdl/lib/misc/utils_pkg.vhd" line 103: VHDL Assertion Statement with non constant condition is ignored.
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Analyzing hierarchy for entity <sdram_ctrl_frontend64_wb> in library <work> (architecture <struct>) with generics.
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BL = 2
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f_sdrclk = 100.000000
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f_sysclk = 100.000000
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fifo_depth = 5
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Analyzing hierarchy for entity <vga_frontend64> in library <work> (architecture <behavioral>) with generics.
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fifo_almost_empty_thresh = 256
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fifo_almost_full_thresh = 1920
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fifo_depth = 2048
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tsvga = (f_pxl_clk => 40000000
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nfps => 60
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ts_h => (ncyc_scan => 800
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ncyc_porch_front => 40
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ncyc_sync_pulse => 128
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ncyc_porch_back => 88
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sync_polarity => '0')
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ts_v => (ncyc_scan => 600
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ncyc_porch_front => 1
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ncyc_sync_pulse => 4
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ncyc_porch_back => 23
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sync_polarity => '0'))
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Analyzing hierarchy for entity <ac97_wb> in library <work> (architecture <behavior>) with generics.
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fifo_depth = 8
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Analyzing hierarchy for entity <ps2_wb> in library <work> (architecture <behavior>) with generics.
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f_sys_clk = 100.000000
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Analyzing hierarchy for entity <ps2_phy> in library <work> (architecture <Behavioral>).
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Analyzing hierarchy for entity <rom> in library <work> (architecture <data>).
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Analyzing hierarchy for entity <uart_tx> in library <work> (architecture <macro_level_definition>).
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Analyzing hierarchy for entity <uart_rx> in library <work> (architecture <macro_level_definition>).
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Analyzing hierarchy for entity <fifo_sync> in library <work> (architecture <Behavioral>) with generics.
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addr_width = 5
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allow_empty_reads = false
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allow_full_writes = false
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almost_empty_thresh = 4
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almost_full_thresh = 12
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data_width = 30
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do_last_read_update = true
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Analyzing hierarchy for entity <fifo_async> in library <work> (architecture <Behavioral>) with generics.
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addr_width = 5
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allow_empty_reads = false
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allow_full_writes = false
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almost_empty_thresh = 4
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almost_full_thresh = 12
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data_width = 72
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do_last_read_update = true
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Analyzing hierarchy for entity <fifo_async> in library <work> (architecture <Behavioral>) with generics.
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addr_width = 5
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allow_empty_reads = false
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allow_full_writes = false
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almost_empty_thresh = 4
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almost_full_thresh = 12
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data_width = 64
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do_last_read_update = true
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Analyzing hierarchy for entity <sdram_ctrl_top> in library <work> (architecture <rtl>) with generics.
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BL = 2
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f_sdrclk = 100.000000
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f_sysclk = 100.000000
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fifo_depth = 5
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Analyzing hierarchy for entity <vga_backend> in library <work> (architecture <Behavioral>) with generics.
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tsvga = (f_pxl_clk => 40000000
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nfps => 60
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ts_h => (ncyc_scan => 800
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ncyc_porch_front => 40
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ncyc_sync_pulse => 128
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ncyc_porch_back => 88
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sync_polarity => '0')
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ts_v => (ncyc_scan => 600
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ncyc_porch_front => 1
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ncyc_sync_pulse => 4
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ncyc_porch_back => 23
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sync_polarity => '0'))
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Analyzing hierarchy for entity <fifo_async> in library <work> (architecture <Behavioral>) with generics.
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addr_width = 11
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allow_empty_reads = false
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allow_full_writes = false
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almost_empty_thresh = 256
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almost_full_thresh = 1920
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data_width = 64
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do_last_read_update = true
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Analyzing hierarchy for entity <fifo_sync> in library <work> (architecture <Behavioral>) with generics.
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addr_width = 9
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allow_empty_reads = false
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allow_full_writes = false
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almost_empty_thresh = 4
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almost_full_thresh = 12
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data_width = 64
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do_last_read_update = true
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Analyzing hierarchy for entity <fifo_sync> in library <work> (architecture <Behavioral>) with generics.
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addr_width = 2
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allow_empty_reads = false
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allow_full_writes = false
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almost_empty_thresh = 4
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almost_full_thresh = 12
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data_width = 105
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do_last_read_update = false
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Analyzing hierarchy for entity <char_gen> in library <work> (architecture <Behavioral>) with generics.
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CHARACTER_SCALE = 1
|
|
CHAR_ROM_DEPTH = 256
|
|
CHAR_ROM_SIZE_X = 8
|
|
CHAR_ROM_SIZE_Y = 16
|
|
CHAR_SPACING_X = 0
|
|
CHAR_SPACING_Y = 0
|
|
MAX_CHAR_PER_LINE = 80
|
|
MAX_LINE_PER_FRAME = 32
|
|
SCREEN_OFFSET_X = 16
|
|
SCREEN_OFFSET_Y = 16
|
|
tsvga = (f_pxl_clk => 40000000
|
|
nfps => 60
|
|
ts_h => (ncyc_scan => 800
|
|
ncyc_porch_front => 40
|
|
ncyc_sync_pulse => 128
|
|
ncyc_porch_back => 88
|
|
sync_polarity => '0')
|
|
ts_v => (ncyc_scan => 600
|
|
ncyc_porch_front => 1
|
|
ncyc_sync_pulse => 4
|
|
ncyc_porch_back => 23
|
|
sync_polarity => '0'))
|
|
|
|
Analyzing hierarchy for entity <fifo_sync> in library <work> (architecture <Behavioral>) with generics.
|
|
addr_width = 8
|
|
allow_empty_reads = false
|
|
allow_full_writes = false
|
|
almost_empty_thresh = 25
|
|
almost_full_thresh = 230
|
|
data_width = 18
|
|
do_last_read_update = true
|
|
|
|
Analyzing hierarchy for entity <ac_io> in library <work> (architecture <Behavioral>).
|
|
|
|
Analyzing hierarchy for entity <ps2_core> in library <work> (architecture <Behavioral>) with generics.
|
|
f_sys_clk = 100.000000
|
|
|
|
Analyzing hierarchy for entity <debounce> in library <work> (architecture <behavioral>) with generics.
|
|
ncyc_latency = 8
|
|
|
|
Analyzing hierarchy for entity <kcuart_tx> in library <work> (architecture <low_level_definition>).
|
|
|
|
Analyzing hierarchy for entity <bbfifo_16x8> in library <work> (architecture <low_level_definition>).
|
|
|
|
Analyzing hierarchy for entity <kcuart_rx> in library <work> (architecture <low_level_definition>).
|
|
|
|
Analyzing hierarchy for entity <fifo_sync_ctrl> in library <work> (architecture <Behavioral>) with generics.
|
|
addr_width = 5
|
|
almost_empty_thresh = 4
|
|
almost_full_thresh = 12
|
|
|
|
Analyzing hierarchy for entity <dpram_1w1r> in library <work> (architecture <Behavioral>) with generics.
|
|
addr_width = 5
|
|
data_width = 30
|
|
|
|
Analyzing hierarchy for entity <fifo_async_ctrl> in library <work> (architecture <Behavioral>) with generics.
|
|
addr_width = 5
|
|
almost_empty_thresh = 4
|
|
almost_full_thresh = 12
|
|
|
|
Analyzing hierarchy for entity <dpram_1w1r> in library <work> (architecture <Behavioral>) with generics.
|
|
addr_width = 5
|
|
data_width = 72
|
|
|
|
Analyzing hierarchy for entity <dpram_1w1r> in library <work> (architecture <Behavioral>) with generics.
|
|
addr_width = 5
|
|
data_width = 64
|
|
|
|
Analyzing hierarchy for entity <sdram_ctrl> in library <work> (architecture <behaviour>) with generics.
|
|
BL = 2
|
|
f_sysclk = 100.000000
|
|
|
|
Analyzing hierarchy for entity <fifo_async> in library <work> (architecture <Behavioral>) with generics.
|
|
addr_width = 5
|
|
allow_empty_reads = false
|
|
allow_full_writes = false
|
|
almost_empty_thresh = 4
|
|
almost_full_thresh = 12
|
|
data_width = 32
|
|
do_last_read_update = true
|
|
|
|
Analyzing hierarchy for entity <sdram_cmd> in library <work> (architecture <behaviour>) with generics.
|
|
BL = 2
|
|
f_sdrclk = 100.000000
|
|
|
|
Analyzing hierarchy for entity <ddr_phy> in library <work> (architecture <tech>).
|
|
|
|
Analyzing hierarchy for entity <vga_timing> in library <work> (architecture <Behavioral>) with generics.
|
|
tsvga = (f_pxl_clk => 40000000
|
|
nfps => 60
|
|
ts_h => (ncyc_scan => 800
|
|
ncyc_porch_front => 40
|
|
ncyc_sync_pulse => 128
|
|
ncyc_porch_back => 88
|
|
sync_polarity => '0')
|
|
ts_v => (ncyc_scan => 600
|
|
ncyc_porch_front => 1
|
|
ncyc_sync_pulse => 4
|
|
ncyc_porch_back => 23
|
|
sync_polarity => '0'))
|
|
|
|
Analyzing hierarchy for entity <fifo_async_ctrl> in library <work> (architecture <Behavioral>) with generics.
|
|
addr_width = 11
|
|
almost_empty_thresh = 256
|
|
almost_full_thresh = 1920
|
|
|
|
Analyzing hierarchy for entity <dpram_1w1r> in library <work> (architecture <Behavioral>) with generics.
|
|
addr_width = 11
|
|
data_width = 64
|
|
|
|
Analyzing hierarchy for entity <fifo_sync_ctrl> in library <work> (architecture <Behavioral>) with generics.
|
|
addr_width = 9
|
|
almost_empty_thresh = 4
|
|
almost_full_thresh = 12
|
|
|
|
Analyzing hierarchy for entity <dpram_1w1r> in library <work> (architecture <Behavioral>) with generics.
|
|
addr_width = 9
|
|
data_width = 64
|
|
|
|
Analyzing hierarchy for entity <fifo_sync_ctrl> in library <work> (architecture <Behavioral>) with generics.
|
|
addr_width = 2
|
|
almost_empty_thresh = 4
|
|
almost_full_thresh = 12
|
|
|
|
Analyzing hierarchy for entity <dpram_1w1r> in library <work> (architecture <Behavioral>) with generics.
|
|
addr_width = 2
|
|
data_width = 105
|
|
|
|
Analyzing hierarchy for entity <char_rom> in library <work> (architecture <RTL>).
|
|
|
|
Analyzing hierarchy for entity <dpram_1w1r> in library <work> (architecture <Behavioral>) with generics.
|
|
addr_width = 12
|
|
data_width = 8
|
|
|
|
Analyzing hierarchy for entity <fifo_sync_ctrl> in library <work> (architecture <Behavioral>) with generics.
|
|
addr_width = 8
|
|
almost_empty_thresh = 25
|
|
almost_full_thresh = 230
|
|
|
|
Analyzing hierarchy for entity <dpram_1w1r> in library <work> (architecture <Behavioral>) with generics.
|
|
addr_width = 8
|
|
data_width = 18
|
|
|
|
Analyzing hierarchy for entity <ac_in> in library <work> (architecture <behavioral>).
|
|
|
|
Analyzing hierarchy for entity <ac_out> in library <work> (architecture <behavioral>).
|
|
|
|
Analyzing hierarchy for entity <gray_counter> in library <work> (architecture <Behavioral>) with generics.
|
|
init_value = 0
|
|
width = 6
|
|
|
|
Analyzing hierarchy for entity <fifo_async_ctrl> in library <work> (architecture <Behavioral>) with generics.
|
|
addr_width = 5
|
|
almost_empty_thresh = 4
|
|
almost_full_thresh = 12
|
|
|
|
Analyzing hierarchy for entity <dpram_1w1r> in library <work> (architecture <Behavioral>) with generics.
|
|
addr_width = 5
|
|
data_width = 32
|
|
|
|
Analyzing hierarchy for entity <vga_sync> in library <work> (architecture <Behavioral>) with generics.
|
|
ts = (ncyc_scan => 800
|
|
ncyc_porch_front => 40
|
|
ncyc_sync_pulse => 128
|
|
ncyc_porch_back => 88
|
|
sync_polarity => '0')
|
|
|
|
Analyzing hierarchy for entity <vga_sync> in library <work> (architecture <Behavioral>) with generics.
|
|
ts = (ncyc_scan => 600
|
|
ncyc_porch_front => 1
|
|
ncyc_sync_pulse => 4
|
|
ncyc_porch_back => 23
|
|
sync_polarity => '0')
|
|
|
|
Analyzing hierarchy for entity <gray_counter> in library <work> (architecture <Behavioral>) with generics.
|
|
init_value = 0
|
|
width = 12
|
|
|
|
Analyzing hierarchy for entity <singleshot> in library <work> (architecture <behavioral>) with generics.
|
|
mode = 0
|
|
|
|
Analyzing hierarchy for entity <singleshot> in library <work> (architecture <behavioral>) with generics.
|
|
mode = 1
|
|
|
|
Analyzing hierarchy for entity <gray_counter> in library <work> (architecture <Behavioral>) with generics.
|
|
init_value = 0
|
|
width = 6
|
|
|
|
WARNING:Xst:2591 - "W:/vhdl/lib/uart/kcuart_tx.vhd" line 221: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
|
|
WARNING:Xst:2591 - "W:/vhdl/lib/uart/kcuart_tx.vhd" line 270: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
|
|
WARNING:Xst:2591 - "W:/vhdl/lib/uart/kcuart_tx.vhd" line 318: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
|
|
WARNING:Xst:2591 - "W:/vhdl/lib/uart/bbfifo_16x8.vhd" line 257: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
|
|
WARNING:Xst:2591 - "W:/vhdl/lib/uart/kcuart_rx.vhd" line 254: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
|
|
WARNING:Xst:2591 - "W:/vhdl/lib/uart/kcuart_tx.vhd" line 133: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
|
|
WARNING:Xst:2591 - "W:/vhdl/lib/uart/kcuart_tx.vhd" line 281: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
|
|
WARNING:Xst:2591 - "W:/vhdl/lib/uart/kcuart_tx.vhd" line 300: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
|
|
WARNING:Xst:2591 - "W:/vhdl/lib/uart/kcuart_tx.vhd" line 354: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
|
|
WARNING:Xst:2591 - "W:/vhdl/lib/uart/bbfifo_16x8.vhd" line 158: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
|
|
WARNING:Xst:2591 - "W:/vhdl/lib/uart/bbfifo_16x8.vhd" line 215: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
|
|
WARNING:Xst:2591 - "W:/vhdl/lib/uart/bbfifo_16x8.vhd" line 226: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
|
|
WARNING:Xst:2591 - "W:/vhdl/lib/uart/bbfifo_16x8.vhd" line 239: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
|
|
WARNING:Xst:2591 - "W:/vhdl/lib/uart/kcuart_rx.vhd" line 236: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
|
|
WARNING:Xst:2591 - "W:/vhdl/lib/uart/kcuart_tx.vhd" line 333: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
|
|
|
|
=========================================================================
|
|
* HDL Analysis *
|
|
=========================================================================
|
|
Analyzing generic Entity <mips_sys> in library <work> (Architecture <behavior>).
|
|
sdram_phaseshift = 0
|
|
sys_freq = 100.000000
|
|
sys_freq_in = 100.000000
|
|
tsvga = (f_pxl_clk => 40000000
|
|
nfps => 60
|
|
ts_h => (ncyc_scan => 800
|
|
ncyc_porch_front => 40
|
|
ncyc_sync_pulse => 128
|
|
ncyc_porch_back => 88
|
|
sync_polarity => '0')
|
|
ts_v => (ncyc_scan => 600
|
|
ncyc_porch_front => 1
|
|
ncyc_sync_pulse => 4
|
|
ncyc_porch_back => 23
|
|
sync_polarity => '0'))
|
|
Set user-defined property "KEEP = TRUE" for signal <cpu_clk>.
|
|
Set user-defined property "KEEP = TRUE" for signal <sdram_clk0>.
|
|
Set user-defined property "KEEP = TRUE" for signal <vga_clk>.
|
|
Set user-defined property "KEEP = TRUE" for signal <CLK_O>.
|
|
Set user-defined property "KEEP = TRUE" for signal <RST_O>.
|
|
WARNING:Xst:2211 - "W:/vhdl/projects/mips_sys/src/mips_sys.vhd" line 678: Instantiating black box module <mips_top>.
|
|
WARNING:Xst:753 - "W:/vhdl/projects/mips_sys/src/mips_sys.vhd" line 715: Unconnected output port 'dout' of component 'lcd_port'.
|
|
WARNING:Xst:753 - "W:/vhdl/projects/mips_sys/src/mips_sys.vhd" line 756: Unconnected output port 'async_be' of component 'async_port_wb'.
|
|
WARNING:Xst:753 - "W:/vhdl/projects/mips_sys/src/mips_sys.vhd" line 789: Unconnected output port 'async_be' of component 'async_port_wb'.
|
|
WARNING:Xst:753 - "W:/vhdl/projects/mips_sys/src/mips_sys.vhd" line 789: Unconnected output port 'async_rst' of component 'async_port_wb'.
|
|
WARNING:Xst:753 - "W:/vhdl/projects/mips_sys/src/mips_sys.vhd" line 863: Unconnected output port 'sdr1_clk0_out' of component 'clockgen'.
|
|
Entity <mips_sys> analyzed. Unit <mips_sys> generated.
|
|
|
|
Analyzing Entity <rom_wb> in library <work> (Architecture <behavior>).
|
|
Entity <rom_wb> analyzed. Unit <rom_wb> generated.
|
|
|
|
Analyzing Entity <rom> in library <work> (Architecture <data>).
|
|
Set user-defined property "JTAG_CHAIN = 1" for instance <BSCAN_VIRTEX4_inst1> in unit <rom>.
|
|
Entity <rom> analyzed. Unit <rom> generated.
|
|
|
|
Analyzing Entity <lcd_port> in library <work> (Architecture <behavioral>).
|
|
Entity <lcd_port> analyzed. Unit <lcd_port> generated.
|
|
|
|
Analyzing generic Entity <gpio_wb> in library <work> (Architecture <behavior>).
|
|
f_sysclk = 100.000000
|
|
Entity <gpio_wb> analyzed. Unit <gpio_wb> generated.
|
|
|
|
Analyzing generic Entity <async_port_wb.1> in library <work> (Architecture <behavioral>).
|
|
addr_width = 25
|
|
async_timespec = (T_leadin => 0.000000
|
|
T_pulse_rd => 120.000000
|
|
T_pulse_wr => 70.000000
|
|
T_leadout => 0.000000
|
|
T_release => 40.000000
|
|
T_pulse_rst => 80.000000
|
|
T_pulse_page_rd => 30.000000
|
|
can_page_rd => true
|
|
nbits_page_rd => 4
|
|
pol_cs => '1'
|
|
pol_oe => '0'
|
|
pol_we => '0'
|
|
pol_be => '0'
|
|
pol_rst => '0')
|
|
byte_sel_width = 1
|
|
data_width = 32
|
|
f_sysclk = 100.000000
|
|
Entity <async_port_wb.1> analyzed. Unit <async_port_wb.1> generated.
|
|
|
|
Analyzing generic Entity <async_port_wb.2> in library <work> (Architecture <behavioral>).
|
|
addr_width = 4
|
|
async_timespec = (T_leadin => 10.000000
|
|
T_pulse_rd => 60.000000
|
|
T_pulse_wr => 60.000000
|
|
T_leadout => 10.000000
|
|
T_release => 80.000000
|
|
T_pulse_rst => 80.000000
|
|
T_pulse_page_rd => 0.000000
|
|
can_page_rd => false
|
|
nbits_page_rd => 0
|
|
pol_cs => '0'
|
|
pol_oe => '0'
|
|
pol_we => '0'
|
|
pol_be => '0'
|
|
pol_rst => '0')
|
|
byte_sel_width = 1
|
|
data_width = 16
|
|
f_sysclk = 100.000000
|
|
Entity <async_port_wb.2> analyzed. Unit <async_port_wb.2> generated.
|
|
|
|
Analyzing generic Entity <uart_wb> in library <work> (Architecture <behavior>).
|
|
simulate_tx = false
|
|
INFO:Xst:2679 - Register <DAT_O<31>> in unit <uart_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
|
|
INFO:Xst:2679 - Register <DAT_O<30>> in unit <uart_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
|
|
INFO:Xst:2679 - Register <DAT_O<29>> in unit <uart_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
|
|
INFO:Xst:2679 - Register <DAT_O<28>> in unit <uart_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
|
|
INFO:Xst:2679 - Register <DAT_O<27>> in unit <uart_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
|
|
INFO:Xst:2679 - Register <DAT_O<26>> in unit <uart_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
|
|
INFO:Xst:2679 - Register <DAT_O<25>> in unit <uart_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
|
|
INFO:Xst:2679 - Register <DAT_O<24>> in unit <uart_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
|
|
INFO:Xst:2679 - Register <DAT_O<23>> in unit <uart_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
|
|
INFO:Xst:2679 - Register <DAT_O<22>> in unit <uart_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
|
|
INFO:Xst:2679 - Register <DAT_O<21>> in unit <uart_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
|
|
INFO:Xst:2679 - Register <DAT_O<20>> in unit <uart_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
|
|
INFO:Xst:2679 - Register <DAT_O<19>> in unit <uart_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
|
|
INFO:Xst:2679 - Register <DAT_O<18>> in unit <uart_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
|
|
INFO:Xst:2679 - Register <DAT_O<17>> in unit <uart_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
|
|
INFO:Xst:2679 - Register <DAT_O<16>> in unit <uart_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
|
|
Entity <uart_wb> analyzed. Unit <uart_wb> generated.
|
|
|
|
Analyzing Entity <uart_tx> in library <work> (Architecture <macro_level_definition>).
|
|
Entity <uart_tx> analyzed. Unit <uart_tx> generated.
|
|
|
|
Analyzing Entity <kcuart_tx> in library <work> (Architecture <low_level_definition>).
|
|
Set user-defined property "INIT = E4FF" for instance <mux1_lut> in unit <kcuart_tx>.
|
|
Set user-defined property "INIT = E4FF" for instance <mux2_lut> in unit <kcuart_tx>.
|
|
Set user-defined property "INIT = E4FF" for instance <mux3_lut> in unit <kcuart_tx>.
|
|
Set user-defined property "INIT = E4FF" for instance <mux4_lut> in unit <kcuart_tx>.
|
|
Set user-defined property "INIT = 0" for instance <pipeline_serial> in unit <kcuart_tx>.
|
|
Set user-defined property "INIT = 0" for instance <count_width_loop[0].register_bit> in unit <kcuart_tx>.
|
|
Set user-defined property "INIT = 8" for instance <count_width_loop[0].count_lut> in unit <kcuart_tx>.
|
|
Set user-defined property "INIT = 0" for instance <count_width_loop[1].register_bit> in unit <kcuart_tx>.
|
|
Set user-defined property "INIT = 8" for instance <count_width_loop[1].count_lut> in unit <kcuart_tx>.
|
|
Set user-defined property "INIT = 0" for instance <count_width_loop[2].register_bit> in unit <kcuart_tx>.
|
|
Set user-defined property "INIT = 8" for instance <count_width_loop[2].count_lut> in unit <kcuart_tx>.
|
|
Set user-defined property "INIT = 10" for instance <ready_lut> in unit <kcuart_tx>.
|
|
Set user-defined property "INIT = 0190" for instance <start_lut> in unit <kcuart_tx>.
|
|
Set user-defined property "INIT = 0" for instance <Tx_start_reg> in unit <kcuart_tx>.
|
|
Set user-defined property "INIT = 1540" for instance <run_lut> in unit <kcuart_tx>.
|
|
Set user-defined property "INIT = 0" for instance <Tx_run_reg> in unit <kcuart_tx>.
|
|
Set user-defined property "INIT = 94" for instance <hot_state_lut> in unit <kcuart_tx>.
|
|
Set user-defined property "INIT = 0" for instance <hot_state_reg> in unit <kcuart_tx>.
|
|
Set user-defined property "INIT = 0000" for instance <delay14_srl> in unit <kcuart_tx>.
|
|
Set user-defined property "INIT = 0" for instance <Tx_bit_reg> in unit <kcuart_tx>.
|
|
Set user-defined property "INIT = 0180" for instance <stop_lut> in unit <kcuart_tx>.
|
|
Set user-defined property "INIT = 0" for instance <Tx_stop_reg> in unit <kcuart_tx>.
|
|
Set user-defined property "INIT = 8" for instance <complete_lut> in unit <kcuart_tx>.
|
|
Set user-defined property "INIT = 0" for instance <Tx_complete_reg> in unit <kcuart_tx>.
|
|
Entity <kcuart_tx> analyzed. Unit <kcuart_tx> generated.
|
|
|
|
Analyzing Entity <bbfifo_16x8> in library <work> (Architecture <low_level_definition>).
|
|
Set user-defined property "INIT = 0000" for instance <data_width_loop[0].data_srl> in unit <bbfifo_16x8>.
|
|
Set user-defined property "INIT = 0000" for instance <data_width_loop[1].data_srl> in unit <bbfifo_16x8>.
|
|
Set user-defined property "INIT = 0000" for instance <data_width_loop[2].data_srl> in unit <bbfifo_16x8>.
|
|
Set user-defined property "INIT = 0000" for instance <data_width_loop[3].data_srl> in unit <bbfifo_16x8>.
|
|
Set user-defined property "INIT = 0000" for instance <data_width_loop[4].data_srl> in unit <bbfifo_16x8>.
|
|
Set user-defined property "INIT = 0000" for instance <data_width_loop[5].data_srl> in unit <bbfifo_16x8>.
|
|
Set user-defined property "INIT = 0000" for instance <data_width_loop[6].data_srl> in unit <bbfifo_16x8>.
|
|
Set user-defined property "INIT = 0000" for instance <data_width_loop[7].data_srl> in unit <bbfifo_16x8>.
|
|
Set user-defined property "INIT = 0" for instance <count_width_loop[0].register_bit> in unit <bbfifo_16x8>.
|
|
Set user-defined property "INIT = 6606" for instance <count_width_loop[0].count_lut> in unit <bbfifo_16x8>.
|
|
Set user-defined property "INIT = 0" for instance <count_width_loop[1].register_bit> in unit <bbfifo_16x8>.
|
|
Set user-defined property "INIT = 6606" for instance <count_width_loop[1].count_lut> in unit <bbfifo_16x8>.
|
|
Set user-defined property "INIT = 0" for instance <count_width_loop[2].register_bit> in unit <bbfifo_16x8>.
|
|
Set user-defined property "INIT = 6606" for instance <count_width_loop[2].count_lut> in unit <bbfifo_16x8>.
|
|
Set user-defined property "INIT = 0" for instance <count_width_loop[3].register_bit> in unit <bbfifo_16x8>.
|
|
Set user-defined property "INIT = 6606" for instance <count_width_loop[3].count_lut> in unit <bbfifo_16x8>.
|
|
Set user-defined property "INIT = 0001" for instance <zero_lut> in unit <bbfifo_16x8>.
|
|
Set user-defined property "INIT = 8000" for instance <full_lut> in unit <bbfifo_16x8>.
|
|
Set user-defined property "INIT = BFA0" for instance <dp_lut> in unit <bbfifo_16x8>.
|
|
Set user-defined property "INIT = 0" for instance <dp_flop> in unit <bbfifo_16x8>.
|
|
Set user-defined property "INIT = C4" for instance <valid_lut> in unit <bbfifo_16x8>.
|
|
Entity <bbfifo_16x8> analyzed. Unit <bbfifo_16x8> generated.
|
|
|
|
Analyzing Entity <uart_rx> in library <work> (Architecture <macro_level_definition>).
|
|
Entity <uart_rx> analyzed. Unit <uart_rx> generated.
|
|
|
|
Analyzing Entity <kcuart_rx> in library <work> (Architecture <low_level_definition>).
|
|
Set user-defined property "INIT = 0" for instance <sync_reg> in unit <kcuart_rx>.
|
|
Set user-defined property "INIT = 0" for instance <stop_reg> in unit <kcuart_rx>.
|
|
Set user-defined property "INIT = 0000" for instance <data_loop[0].lsbs.delay15_srl> in unit <kcuart_rx>.
|
|
Set user-defined property "INIT = 0" for instance <data_loop[0].data_reg> in unit <kcuart_rx>.
|
|
Set user-defined property "INIT = 0000" for instance <data_loop[1].lsbs.delay15_srl> in unit <kcuart_rx>.
|
|
Set user-defined property "INIT = 0" for instance <data_loop[1].data_reg> in unit <kcuart_rx>.
|
|
Set user-defined property "INIT = 0000" for instance <data_loop[2].lsbs.delay15_srl> in unit <kcuart_rx>.
|
|
Set user-defined property "INIT = 0" for instance <data_loop[2].data_reg> in unit <kcuart_rx>.
|
|
Set user-defined property "INIT = 0000" for instance <data_loop[3].lsbs.delay15_srl> in unit <kcuart_rx>.
|
|
Set user-defined property "INIT = 0" for instance <data_loop[3].data_reg> in unit <kcuart_rx>.
|
|
Set user-defined property "INIT = 0000" for instance <data_loop[4].lsbs.delay15_srl> in unit <kcuart_rx>.
|
|
Set user-defined property "INIT = 0" for instance <data_loop[4].data_reg> in unit <kcuart_rx>.
|
|
Set user-defined property "INIT = 0000" for instance <data_loop[5].lsbs.delay15_srl> in unit <kcuart_rx>.
|
|
Set user-defined property "INIT = 0" for instance <data_loop[5].data_reg> in unit <kcuart_rx>.
|
|
Set user-defined property "INIT = 0000" for instance <data_loop[6].lsbs.delay15_srl> in unit <kcuart_rx>.
|
|
Set user-defined property "INIT = 0" for instance <data_loop[6].data_reg> in unit <kcuart_rx>.
|
|
Set user-defined property "INIT = 0000" for instance <data_loop[7].msb.delay15_srl> in unit <kcuart_rx>.
|
|
Set user-defined property "INIT = 0" for instance <data_loop[7].data_reg> in unit <kcuart_rx>.
|
|
Set user-defined property "INIT = 0000" for instance <start_srl> in unit <kcuart_rx>.
|
|
Set user-defined property "INIT = 0" for instance <start_reg> in unit <kcuart_rx>.
|
|
Set user-defined property "INIT = 0000" for instance <edge_srl> in unit <kcuart_rx>.
|
|
Set user-defined property "INIT = 0" for instance <edge_reg> in unit <kcuart_rx>.
|
|
Set user-defined property "INIT = 0040" for instance <valid_lut> in unit <kcuart_rx>.
|
|
Set user-defined property "INIT = 0" for instance <valid_reg> in unit <kcuart_rx>.
|
|
Set user-defined property "INIT = 54" for instance <purge_lut> in unit <kcuart_rx>.
|
|
Set user-defined property "INIT = 0" for instance <purge_reg> in unit <kcuart_rx>.
|
|
Set user-defined property "INIT = 0000" for instance <valid_loop[0].lsb.delay15_srl> in unit <kcuart_rx>.
|
|
Set user-defined property "INIT = 0" for instance <valid_loop[0].data_reg> in unit <kcuart_rx>.
|
|
Set user-defined property "INIT = 0000" for instance <valid_loop[1].msbs.delay16_srl> in unit <kcuart_rx>.
|
|
Set user-defined property "INIT = 0" for instance <valid_loop[1].data_reg> in unit <kcuart_rx>.
|
|
Set user-defined property "INIT = 0000" for instance <valid_loop[2].msbs.delay16_srl> in unit <kcuart_rx>.
|
|
Set user-defined property "INIT = 0" for instance <valid_loop[2].data_reg> in unit <kcuart_rx>.
|
|
Set user-defined property "INIT = 0000" for instance <valid_loop[3].msbs.delay16_srl> in unit <kcuart_rx>.
|
|
Set user-defined property "INIT = 0" for instance <valid_loop[3].data_reg> in unit <kcuart_rx>.
|
|
Set user-defined property "INIT = 0000" for instance <valid_loop[4].msbs.delay16_srl> in unit <kcuart_rx>.
|
|
Set user-defined property "INIT = 0" for instance <valid_loop[4].data_reg> in unit <kcuart_rx>.
|
|
Set user-defined property "INIT = 0000" for instance <valid_loop[5].msbs.delay16_srl> in unit <kcuart_rx>.
|
|
Set user-defined property "INIT = 0" for instance <valid_loop[5].data_reg> in unit <kcuart_rx>.
|
|
Set user-defined property "INIT = 0000" for instance <valid_loop[6].msbs.delay16_srl> in unit <kcuart_rx>.
|
|
Set user-defined property "INIT = 0" for instance <valid_loop[6].data_reg> in unit <kcuart_rx>.
|
|
Set user-defined property "INIT = 0000" for instance <valid_loop[7].msbs.delay16_srl> in unit <kcuart_rx>.
|
|
Set user-defined property "INIT = 0" for instance <valid_loop[7].data_reg> in unit <kcuart_rx>.
|
|
Set user-defined property "INIT = 0000" for instance <valid_loop[8].msbs.delay16_srl> in unit <kcuart_rx>.
|
|
Set user-defined property "INIT = 0" for instance <valid_loop[8].data_reg> in unit <kcuart_rx>.
|
|
Set user-defined property "INIT = 8" for instance <strobe_lut> in unit <kcuart_rx>.
|
|
Set user-defined property "INIT = 0" for instance <strobe_reg> in unit <kcuart_rx>.
|
|
Entity <kcuart_rx> analyzed. Unit <kcuart_rx> generated.
|
|
|
|
Analyzing generic Entity <clockgen> in library <work> (Architecture <tech>).
|
|
clk_in_freq = 100.000000
|
|
sdr0_clk_out_phaseshift = 0
|
|
sdr1_clk_out_phaseshift = 0
|
|
sys_clk_out_freq = 100.000000
|
|
vga_clk_out_freq = 40.000000
|
|
Set user-defined property "CLKDV_DIVIDE = 2.0000000000000000" for instance <inst_DCM_VGA_FX> in unit <clockgen>.
|
|
Set user-defined property "CLKFX_DIVIDE = 5" for instance <inst_DCM_VGA_FX> in unit <clockgen>.
|
|
Set user-defined property "CLKFX_MULTIPLY = 2" for instance <inst_DCM_VGA_FX> in unit <clockgen>.
|
|
Set user-defined property "CLKIN_DIVIDE_BY_2 = FALSE" for instance <inst_DCM_VGA_FX> in unit <clockgen>.
|
|
Set user-defined property "CLKIN_PERIOD = 10.0000000000000000" for instance <inst_DCM_VGA_FX> in unit <clockgen>.
|
|
Set user-defined property "CLKOUT_PHASE_SHIFT = NONE" for instance <inst_DCM_VGA_FX> in unit <clockgen>.
|
|
Set user-defined property "CLK_FEEDBACK = 1X" for instance <inst_DCM_VGA_FX> in unit <clockgen>.
|
|
Set user-defined property "DCM_AUTOCALIBRATION = TRUE" for instance <inst_DCM_VGA_FX> in unit <clockgen>.
|
|
Set user-defined property "DCM_PERFORMANCE_MODE = MAX_SPEED" for instance <inst_DCM_VGA_FX> in unit <clockgen>.
|
|
Set user-defined property "DESKEW_ADJUST = SOURCE_SYNCHRONOUS" for instance <inst_DCM_VGA_FX> in unit <clockgen>.
|
|
Set user-defined property "DFS_FREQUENCY_MODE = LOW" for instance <inst_DCM_VGA_FX> in unit <clockgen>.
|
|
Set user-defined property "DLL_FREQUENCY_MODE = LOW" for instance <inst_DCM_VGA_FX> in unit <clockgen>.
|
|
Set user-defined property "DUTY_CYCLE_CORRECTION = TRUE" for instance <inst_DCM_VGA_FX> in unit <clockgen>.
|
|
Set user-defined property "FACTORY_JF = F0F0" for instance <inst_DCM_VGA_FX> in unit <clockgen>.
|
|
Set user-defined property "PHASE_SHIFT = 0" for instance <inst_DCM_VGA_FX> in unit <clockgen>.
|
|
Set user-defined property "STARTUP_WAIT = FALSE" for instance <inst_DCM_VGA_FX> in unit <clockgen>.
|
|
Set user-defined property "CLKDV_DIVIDE = 2.0000000000000000" for instance <inst_DCM_SYS_FX> in unit <clockgen>.
|
|
Set user-defined property "CLKFX_DIVIDE = 2" for instance <inst_DCM_SYS_FX> in unit <clockgen>.
|
|
Set user-defined property "CLKFX_MULTIPLY = 2" for instance <inst_DCM_SYS_FX> in unit <clockgen>.
|
|
Set user-defined property "CLKIN_DIVIDE_BY_2 = FALSE" for instance <inst_DCM_SYS_FX> in unit <clockgen>.
|
|
Set user-defined property "CLKIN_PERIOD = 10.0000000000000000" for instance <inst_DCM_SYS_FX> in unit <clockgen>.
|
|
Set user-defined property "CLKOUT_PHASE_SHIFT = NONE" for instance <inst_DCM_SYS_FX> in unit <clockgen>.
|
|
Set user-defined property "CLK_FEEDBACK = 1X" for instance <inst_DCM_SYS_FX> in unit <clockgen>.
|
|
Set user-defined property "DCM_AUTOCALIBRATION = TRUE" for instance <inst_DCM_SYS_FX> in unit <clockgen>.
|
|
Set user-defined property "DCM_PERFORMANCE_MODE = MAX_SPEED" for instance <inst_DCM_SYS_FX> in unit <clockgen>.
|
|
Set user-defined property "DESKEW_ADJUST = SOURCE_SYNCHRONOUS" for instance <inst_DCM_SYS_FX> in unit <clockgen>.
|
|
Set user-defined property "DFS_FREQUENCY_MODE = LOW" for instance <inst_DCM_SYS_FX> in unit <clockgen>.
|
|
Set user-defined property "DLL_FREQUENCY_MODE = LOW" for instance <inst_DCM_SYS_FX> in unit <clockgen>.
|
|
Set user-defined property "DUTY_CYCLE_CORRECTION = TRUE" for instance <inst_DCM_SYS_FX> in unit <clockgen>.
|
|
Set user-defined property "FACTORY_JF = F0F0" for instance <inst_DCM_SYS_FX> in unit <clockgen>.
|
|
Set user-defined property "PHASE_SHIFT = 0" for instance <inst_DCM_SYS_FX> in unit <clockgen>.
|
|
Set user-defined property "STARTUP_WAIT = FALSE" for instance <inst_DCM_SYS_FX> in unit <clockgen>.
|
|
Set user-defined property "CLKDV_DIVIDE = 2.0000000000000000" for instance <inst_DCM_SDRCLK_0> in unit <clockgen>.
|
|
Set user-defined property "CLKFX_DIVIDE = 1" for instance <inst_DCM_SDRCLK_0> in unit <clockgen>.
|
|
Set user-defined property "CLKFX_MULTIPLY = 4" for instance <inst_DCM_SDRCLK_0> in unit <clockgen>.
|
|
Set user-defined property "CLKIN_DIVIDE_BY_2 = FALSE" for instance <inst_DCM_SDRCLK_0> in unit <clockgen>.
|
|
Set user-defined property "CLKIN_PERIOD = 10.0000000000000000" for instance <inst_DCM_SDRCLK_0> in unit <clockgen>.
|
|
Set user-defined property "CLKOUT_PHASE_SHIFT = FIXED" for instance <inst_DCM_SDRCLK_0> in unit <clockgen>.
|
|
Set user-defined property "CLK_FEEDBACK = 1X" for instance <inst_DCM_SDRCLK_0> in unit <clockgen>.
|
|
Set user-defined property "DCM_AUTOCALIBRATION = TRUE" for instance <inst_DCM_SDRCLK_0> in unit <clockgen>.
|
|
Set user-defined property "DCM_PERFORMANCE_MODE = MAX_SPEED" for instance <inst_DCM_SDRCLK_0> in unit <clockgen>.
|
|
Set user-defined property "DESKEW_ADJUST = SOURCE_SYNCHRONOUS" for instance <inst_DCM_SDRCLK_0> in unit <clockgen>.
|
|
Set user-defined property "DFS_FREQUENCY_MODE = LOW" for instance <inst_DCM_SDRCLK_0> in unit <clockgen>.
|
|
Set user-defined property "DLL_FREQUENCY_MODE = LOW" for instance <inst_DCM_SDRCLK_0> in unit <clockgen>.
|
|
Set user-defined property "DUTY_CYCLE_CORRECTION = TRUE" for instance <inst_DCM_SDRCLK_0> in unit <clockgen>.
|
|
Set user-defined property "FACTORY_JF = F0F0" for instance <inst_DCM_SDRCLK_0> in unit <clockgen>.
|
|
Set user-defined property "PHASE_SHIFT = 0" for instance <inst_DCM_SDRCLK_0> in unit <clockgen>.
|
|
Set user-defined property "STARTUP_WAIT = FALSE" for instance <inst_DCM_SDRCLK_0> in unit <clockgen>.
|
|
Set user-defined property "CLKDV_DIVIDE = 2.0000000000000000" for instance <inst_DCM_SDRCLK_1> in unit <clockgen>.
|
|
Set user-defined property "CLKFX_DIVIDE = 1" for instance <inst_DCM_SDRCLK_1> in unit <clockgen>.
|
|
Set user-defined property "CLKFX_MULTIPLY = 4" for instance <inst_DCM_SDRCLK_1> in unit <clockgen>.
|
|
Set user-defined property "CLKIN_DIVIDE_BY_2 = FALSE" for instance <inst_DCM_SDRCLK_1> in unit <clockgen>.
|
|
Set user-defined property "CLKIN_PERIOD = 10.0000000000000000" for instance <inst_DCM_SDRCLK_1> in unit <clockgen>.
|
|
Set user-defined property "CLKOUT_PHASE_SHIFT = FIXED" for instance <inst_DCM_SDRCLK_1> in unit <clockgen>.
|
|
Set user-defined property "CLK_FEEDBACK = 1X" for instance <inst_DCM_SDRCLK_1> in unit <clockgen>.
|
|
Set user-defined property "DCM_AUTOCALIBRATION = TRUE" for instance <inst_DCM_SDRCLK_1> in unit <clockgen>.
|
|
Set user-defined property "DCM_PERFORMANCE_MODE = MAX_SPEED" for instance <inst_DCM_SDRCLK_1> in unit <clockgen>.
|
|
Set user-defined property "DESKEW_ADJUST = SYSTEM_SYNCHRONOUS" for instance <inst_DCM_SDRCLK_1> in unit <clockgen>.
|
|
Set user-defined property "DFS_FREQUENCY_MODE = LOW" for instance <inst_DCM_SDRCLK_1> in unit <clockgen>.
|
|
Set user-defined property "DLL_FREQUENCY_MODE = LOW" for instance <inst_DCM_SDRCLK_1> in unit <clockgen>.
|
|
Set user-defined property "DUTY_CYCLE_CORRECTION = TRUE" for instance <inst_DCM_SDRCLK_1> in unit <clockgen>.
|
|
Set user-defined property "FACTORY_JF = F0F0" for instance <inst_DCM_SDRCLK_1> in unit <clockgen>.
|
|
Set user-defined property "PHASE_SHIFT = 0" for instance <inst_DCM_SDRCLK_1> in unit <clockgen>.
|
|
Set user-defined property "STARTUP_WAIT = FALSE" for instance <inst_DCM_SDRCLK_1> in unit <clockgen>.
|
|
WARNING:Xst:819 - "W:/vhdl/projects/mips_sys/src/clockgen_virtex4.vhd" line 345: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
|
|
<sdr0_lock>, <sdr1_lock>, <sys_fx_lock>, <vga_fx_lock>
|
|
Entity <clockgen> analyzed. Unit <clockgen> generated.
|
|
|
|
Analyzing generic Entity <sdram_ctrl_frontend64_wb> in library <work> (Architecture <struct>).
|
|
BL = 2
|
|
f_sdrclk = 100.000000
|
|
f_sysclk = 100.000000
|
|
fifo_depth = 5
|
|
WARNING:Xst:753 - "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd" line 139: Unconnected output port 'fifo_afull' of component 'fifo_sync'.
|
|
WARNING:Xst:753 - "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd" line 139: Unconnected output port 'fifo_aempty' of component 'fifo_sync'.
|
|
WARNING:Xst:753 - "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd" line 160: Unconnected output port 'fifo_afull' of component 'fifo_async'.
|
|
WARNING:Xst:753 - "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd" line 160: Unconnected output port 'fifo_aempty' of component 'fifo_async'.
|
|
WARNING:Xst:753 - "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd" line 182: Unconnected output port 'fifo_afull' of component 'fifo_async'.
|
|
WARNING:Xst:753 - "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd" line 182: Unconnected output port 'fifo_aempty' of component 'fifo_async'.
|
|
Entity <sdram_ctrl_frontend64_wb> analyzed. Unit <sdram_ctrl_frontend64_wb> generated.
|
|
|
|
Analyzing generic Entity <fifo_sync.1> in library <work> (Architecture <Behavioral>).
|
|
addr_width = 5
|
|
allow_empty_reads = false
|
|
allow_full_writes = false
|
|
almost_empty_thresh = 4
|
|
almost_full_thresh = 12
|
|
data_width = 30
|
|
do_last_read_update = true
|
|
Entity <fifo_sync.1> analyzed. Unit <fifo_sync.1> generated.
|
|
|
|
Analyzing generic Entity <fifo_sync_ctrl.1> in library <work> (Architecture <Behavioral>).
|
|
addr_width = 5
|
|
almost_empty_thresh = 4
|
|
almost_full_thresh = 12
|
|
Entity <fifo_sync_ctrl.1> analyzed. Unit <fifo_sync_ctrl.1> generated.
|
|
|
|
Analyzing generic Entity <dpram_1w1r.1> in library <work> (Architecture <Behavioral>).
|
|
addr_width = 5
|
|
data_width = 30
|
|
Entity <dpram_1w1r.1> analyzed. Unit <dpram_1w1r.1> generated.
|
|
|
|
Analyzing generic Entity <fifo_async.1> in library <work> (Architecture <Behavioral>).
|
|
addr_width = 5
|
|
allow_empty_reads = false
|
|
allow_full_writes = false
|
|
almost_empty_thresh = 4
|
|
almost_full_thresh = 12
|
|
data_width = 72
|
|
do_last_read_update = true
|
|
Entity <fifo_async.1> analyzed. Unit <fifo_async.1> generated.
|
|
|
|
Analyzing generic Entity <fifo_async_ctrl.1> in library <work> (Architecture <Behavioral>).
|
|
addr_width = 5
|
|
almost_empty_thresh = 4
|
|
almost_full_thresh = 12
|
|
Entity <fifo_async_ctrl.1> analyzed. Unit <fifo_async_ctrl.1> generated.
|
|
|
|
Analyzing generic Entity <gray_counter.1> in library <work> (Architecture <Behavioral>).
|
|
init_value = 0
|
|
width = 6
|
|
Entity <gray_counter.1> analyzed. Unit <gray_counter.1> generated.
|
|
|
|
Analyzing generic Entity <dpram_1w1r.2> in library <work> (Architecture <Behavioral>).
|
|
addr_width = 5
|
|
data_width = 72
|
|
Entity <dpram_1w1r.2> analyzed. Unit <dpram_1w1r.2> generated.
|
|
|
|
Analyzing generic Entity <fifo_async.2> in library <work> (Architecture <Behavioral>).
|
|
addr_width = 5
|
|
allow_empty_reads = false
|
|
allow_full_writes = false
|
|
almost_empty_thresh = 4
|
|
almost_full_thresh = 12
|
|
data_width = 64
|
|
do_last_read_update = true
|
|
Entity <fifo_async.2> analyzed. Unit <fifo_async.2> generated.
|
|
|
|
Analyzing generic Entity <dpram_1w1r.3> in library <work> (Architecture <Behavioral>).
|
|
addr_width = 5
|
|
data_width = 64
|
|
Entity <dpram_1w1r.3> analyzed. Unit <dpram_1w1r.3> generated.
|
|
|
|
Analyzing generic Entity <sdram_ctrl_top> in library <work> (Architecture <rtl>).
|
|
BL = 2
|
|
f_sdrclk = 100.000000
|
|
f_sysclk = 100.000000
|
|
fifo_depth = 5
|
|
WARNING:Xst:753 - "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd" line 158: Unconnected output port 'fifo_afull' of component 'fifo_async'.
|
|
WARNING:Xst:753 - "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd" line 158: Unconnected output port 'fifo_aempty' of component 'fifo_async'.
|
|
Entity <sdram_ctrl_top> analyzed. Unit <sdram_ctrl_top> generated.
|
|
|
|
Analyzing generic Entity <sdram_ctrl> in library <work> (Architecture <behaviour>).
|
|
BL = 2
|
|
f_sysclk = 100.000000
|
|
Entity <sdram_ctrl> analyzed. Unit <sdram_ctrl> generated.
|
|
|
|
Analyzing generic Entity <fifo_async.4> in library <work> (Architecture <Behavioral>).
|
|
addr_width = 5
|
|
allow_empty_reads = false
|
|
allow_full_writes = false
|
|
almost_empty_thresh = 4
|
|
almost_full_thresh = 12
|
|
data_width = 32
|
|
do_last_read_update = true
|
|
Entity <fifo_async.4> analyzed. Unit <fifo_async.4> generated.
|
|
|
|
Analyzing generic Entity <dpram_1w1r.9> in library <work> (Architecture <Behavioral>).
|
|
addr_width = 5
|
|
data_width = 32
|
|
Entity <dpram_1w1r.9> analyzed. Unit <dpram_1w1r.9> generated.
|
|
|
|
Analyzing generic Entity <sdram_cmd> in library <work> (Architecture <behaviour>).
|
|
BL = 2
|
|
f_sdrclk = 100.000000
|
|
Entity <sdram_cmd> analyzed. Unit <sdram_cmd> generated.
|
|
|
|
Analyzing Entity <ddr_phy> in library <work> (Architecture <tech>).
|
|
Set user-defined property "DDR_CLK_EDGE = OPPOSITE_EDGE" for instance <ODDR_clk_p> in unit <ddr_phy>.
|
|
Set user-defined property "INIT = 0" for instance <ODDR_clk_p> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <ODDR_clk_p> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = OPPOSITE_EDGE" for instance <ODDR_clk_n> in unit <ddr_phy>.
|
|
Set user-defined property "INIT = 0" for instance <ODDR_clk_n> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <ODDR_clk_n> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_out[0].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT = 0" for instance <gen_ddr_data_out[0].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_out[0].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_out[1].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT = 0" for instance <gen_ddr_data_out[1].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_out[1].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_out[2].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT = 0" for instance <gen_ddr_data_out[2].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_out[2].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_out[3].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT = 0" for instance <gen_ddr_data_out[3].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_out[3].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_out[4].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT = 0" for instance <gen_ddr_data_out[4].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_out[4].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_out[5].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT = 0" for instance <gen_ddr_data_out[5].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_out[5].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_out[6].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT = 0" for instance <gen_ddr_data_out[6].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_out[6].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_out[7].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT = 0" for instance <gen_ddr_data_out[7].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_out[7].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_out[8].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT = 0" for instance <gen_ddr_data_out[8].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_out[8].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_out[9].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT = 0" for instance <gen_ddr_data_out[9].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_out[9].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_out[10].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT = 0" for instance <gen_ddr_data_out[10].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_out[10].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_out[11].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT = 0" for instance <gen_ddr_data_out[11].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_out[11].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_out[12].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT = 0" for instance <gen_ddr_data_out[12].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_out[12].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_out[13].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT = 0" for instance <gen_ddr_data_out[13].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_out[13].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_out[14].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT = 0" for instance <gen_ddr_data_out[14].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_out[14].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_out[15].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT = 0" for instance <gen_ddr_data_out[15].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_out[15].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_out[16].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT = 0" for instance <gen_ddr_data_out[16].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_out[16].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_out[17].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT = 0" for instance <gen_ddr_data_out[17].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_out[17].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_out[18].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT = 0" for instance <gen_ddr_data_out[18].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_out[18].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_out[19].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT = 0" for instance <gen_ddr_data_out[19].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_out[19].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_out[20].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT = 0" for instance <gen_ddr_data_out[20].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_out[20].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_out[21].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT = 0" for instance <gen_ddr_data_out[21].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_out[21].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_out[22].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT = 0" for instance <gen_ddr_data_out[22].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_out[22].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_out[23].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT = 0" for instance <gen_ddr_data_out[23].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_out[23].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_out[24].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT = 0" for instance <gen_ddr_data_out[24].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_out[24].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_out[25].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT = 0" for instance <gen_ddr_data_out[25].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_out[25].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_out[26].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT = 0" for instance <gen_ddr_data_out[26].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_out[26].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_out[27].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT = 0" for instance <gen_ddr_data_out[27].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_out[27].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_out[28].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT = 0" for instance <gen_ddr_data_out[28].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_out[28].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_out[29].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT = 0" for instance <gen_ddr_data_out[29].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_out[29].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_out[30].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT = 0" for instance <gen_ddr_data_out[30].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_out[30].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_out[31].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT = 0" for instance <gen_ddr_data_out[31].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_out[31].ODDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_dm_out[0].ODDR_dm> in unit <ddr_phy>.
|
|
Set user-defined property "INIT = 0" for instance <gen_ddr_dm_out[0].ODDR_dm> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_dm_out[0].ODDR_dm> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_dm_out[1].ODDR_dm> in unit <ddr_phy>.
|
|
Set user-defined property "INIT = 0" for instance <gen_ddr_dm_out[1].ODDR_dm> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_dm_out[1].ODDR_dm> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_dm_out[2].ODDR_dm> in unit <ddr_phy>.
|
|
Set user-defined property "INIT = 0" for instance <gen_ddr_dm_out[2].ODDR_dm> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_dm_out[2].ODDR_dm> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_dm_out[3].ODDR_dm> in unit <ddr_phy>.
|
|
Set user-defined property "INIT = 0" for instance <gen_ddr_dm_out[3].ODDR_dm> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_dm_out[3].ODDR_dm> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = OPPOSITE_EDGE" for instance <gen_dqs_out[0].ODDR_dqs> in unit <ddr_phy>.
|
|
Set user-defined property "INIT = 0" for instance <gen_dqs_out[0].ODDR_dqs> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_dqs_out[0].ODDR_dqs> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = OPPOSITE_EDGE" for instance <gen_dqs_out[1].ODDR_dqs> in unit <ddr_phy>.
|
|
Set user-defined property "INIT = 0" for instance <gen_dqs_out[1].ODDR_dqs> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_dqs_out[1].ODDR_dqs> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = OPPOSITE_EDGE" for instance <gen_dqs_out[2].ODDR_dqs> in unit <ddr_phy>.
|
|
Set user-defined property "INIT = 0" for instance <gen_dqs_out[2].ODDR_dqs> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_dqs_out[2].ODDR_dqs> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = OPPOSITE_EDGE" for instance <gen_dqs_out[3].ODDR_dqs> in unit <ddr_phy>.
|
|
Set user-defined property "INIT = 0" for instance <gen_dqs_out[3].ODDR_dqs> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_dqs_out[3].ODDR_dqs> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_in[0].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q1 = 0" for instance <gen_ddr_data_in[0].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q2 = 0" for instance <gen_ddr_data_in[0].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_in[0].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_in[1].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q1 = 0" for instance <gen_ddr_data_in[1].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q2 = 0" for instance <gen_ddr_data_in[1].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_in[1].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_in[2].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q1 = 0" for instance <gen_ddr_data_in[2].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q2 = 0" for instance <gen_ddr_data_in[2].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_in[2].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_in[3].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q1 = 0" for instance <gen_ddr_data_in[3].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q2 = 0" for instance <gen_ddr_data_in[3].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_in[3].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_in[4].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q1 = 0" for instance <gen_ddr_data_in[4].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q2 = 0" for instance <gen_ddr_data_in[4].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_in[4].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_in[5].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q1 = 0" for instance <gen_ddr_data_in[5].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q2 = 0" for instance <gen_ddr_data_in[5].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_in[5].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_in[6].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q1 = 0" for instance <gen_ddr_data_in[6].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q2 = 0" for instance <gen_ddr_data_in[6].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_in[6].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_in[7].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q1 = 0" for instance <gen_ddr_data_in[7].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q2 = 0" for instance <gen_ddr_data_in[7].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_in[7].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_in[8].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q1 = 0" for instance <gen_ddr_data_in[8].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q2 = 0" for instance <gen_ddr_data_in[8].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_in[8].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_in[9].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q1 = 0" for instance <gen_ddr_data_in[9].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q2 = 0" for instance <gen_ddr_data_in[9].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_in[9].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_in[10].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q1 = 0" for instance <gen_ddr_data_in[10].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q2 = 0" for instance <gen_ddr_data_in[10].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_in[10].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_in[11].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q1 = 0" for instance <gen_ddr_data_in[11].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q2 = 0" for instance <gen_ddr_data_in[11].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_in[11].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_in[12].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q1 = 0" for instance <gen_ddr_data_in[12].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q2 = 0" for instance <gen_ddr_data_in[12].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_in[12].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_in[13].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q1 = 0" for instance <gen_ddr_data_in[13].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q2 = 0" for instance <gen_ddr_data_in[13].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_in[13].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_in[14].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q1 = 0" for instance <gen_ddr_data_in[14].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q2 = 0" for instance <gen_ddr_data_in[14].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_in[14].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_in[15].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q1 = 0" for instance <gen_ddr_data_in[15].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q2 = 0" for instance <gen_ddr_data_in[15].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_in[15].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_in[16].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q1 = 0" for instance <gen_ddr_data_in[16].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q2 = 0" for instance <gen_ddr_data_in[16].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_in[16].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_in[17].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q1 = 0" for instance <gen_ddr_data_in[17].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q2 = 0" for instance <gen_ddr_data_in[17].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_in[17].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_in[18].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q1 = 0" for instance <gen_ddr_data_in[18].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q2 = 0" for instance <gen_ddr_data_in[18].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_in[18].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_in[19].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q1 = 0" for instance <gen_ddr_data_in[19].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q2 = 0" for instance <gen_ddr_data_in[19].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_in[19].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_in[20].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q1 = 0" for instance <gen_ddr_data_in[20].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q2 = 0" for instance <gen_ddr_data_in[20].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_in[20].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_in[21].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q1 = 0" for instance <gen_ddr_data_in[21].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q2 = 0" for instance <gen_ddr_data_in[21].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_in[21].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_in[22].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q1 = 0" for instance <gen_ddr_data_in[22].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q2 = 0" for instance <gen_ddr_data_in[22].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_in[22].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_in[23].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q1 = 0" for instance <gen_ddr_data_in[23].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q2 = 0" for instance <gen_ddr_data_in[23].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_in[23].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_in[24].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q1 = 0" for instance <gen_ddr_data_in[24].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q2 = 0" for instance <gen_ddr_data_in[24].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_in[24].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_in[25].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q1 = 0" for instance <gen_ddr_data_in[25].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q2 = 0" for instance <gen_ddr_data_in[25].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_in[25].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_in[26].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q1 = 0" for instance <gen_ddr_data_in[26].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q2 = 0" for instance <gen_ddr_data_in[26].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_in[26].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_in[27].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q1 = 0" for instance <gen_ddr_data_in[27].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q2 = 0" for instance <gen_ddr_data_in[27].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_in[27].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_in[28].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q1 = 0" for instance <gen_ddr_data_in[28].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q2 = 0" for instance <gen_ddr_data_in[28].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_in[28].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_in[29].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q1 = 0" for instance <gen_ddr_data_in[29].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q2 = 0" for instance <gen_ddr_data_in[29].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_in[29].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_in[30].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q1 = 0" for instance <gen_ddr_data_in[30].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q2 = 0" for instance <gen_ddr_data_in[30].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_in[30].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance <gen_ddr_data_in[31].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q1 = 0" for instance <gen_ddr_data_in[31].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "INIT_Q2 = 0" for instance <gen_ddr_data_in[31].IDDR_data> in unit <ddr_phy>.
|
|
Set user-defined property "SRTYPE = SYNC" for instance <gen_ddr_data_in[31].IDDR_data> in unit <ddr_phy>.
|
|
Entity <ddr_phy> analyzed. Unit <ddr_phy> generated.
|
|
|
|
Analyzing generic Entity <vga_frontend64> in library <work> (Architecture <behavioral>).
|
|
fifo_almost_empty_thresh = 256
|
|
fifo_almost_full_thresh = 1920
|
|
fifo_depth = 2048
|
|
tsvga = (f_pxl_clk => 40000000
|
|
nfps => 60
|
|
ts_h => (ncyc_scan => 800
|
|
ncyc_porch_front => 40
|
|
ncyc_sync_pulse => 128
|
|
ncyc_porch_back => 88
|
|
sync_polarity => '0')
|
|
ts_v => (ncyc_scan => 600
|
|
ncyc_porch_front => 1
|
|
ncyc_sync_pulse => 4
|
|
ncyc_porch_back => 23
|
|
sync_polarity => '0'))
|
|
WARNING:Xst:753 - "W:/vhdl/lib/VGA_ctrl/src/vga_frontend64.vhd" line 366: Unconnected output port 'fifo_afull' of component 'fifo_sync'.
|
|
WARNING:Xst:753 - "W:/vhdl/lib/VGA_ctrl/src/vga_frontend64.vhd" line 366: Unconnected output port 'fifo_aempty' of component 'fifo_sync'.
|
|
WARNING:Xst:753 - "W:/vhdl/lib/VGA_ctrl/src/vga_frontend64.vhd" line 392: Unconnected output port 'fifo_afull' of component 'fifo_sync'.
|
|
WARNING:Xst:753 - "W:/vhdl/lib/VGA_ctrl/src/vga_frontend64.vhd" line 392: Unconnected output port 'fifo_aempty' of component 'fifo_sync'.
|
|
WARNING:Xst:819 - "W:/vhdl/lib/VGA_ctrl/src/vga_frontend64.vhd" line 436: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
|
|
<blit_request>
|
|
Entity <vga_frontend64> analyzed. Unit <vga_frontend64> generated.
|
|
|
|
Analyzing generic Entity <vga_backend> in library <work> (Architecture <Behavioral>).
|
|
tsvga = (f_pxl_clk => 40000000
|
|
nfps => 60
|
|
ts_h => (ncyc_scan => 800
|
|
ncyc_porch_front => 40
|
|
ncyc_sync_pulse => 128
|
|
ncyc_porch_back => 88
|
|
sync_polarity => '0')
|
|
ts_v => (ncyc_scan => 600
|
|
ncyc_porch_front => 1
|
|
ncyc_sync_pulse => 4
|
|
ncyc_porch_back => 23
|
|
sync_polarity => '0'))
|
|
Entity <vga_backend> analyzed. Unit <vga_backend> generated.
|
|
|
|
Analyzing generic Entity <vga_timing> in library <work> (Architecture <Behavioral>).
|
|
tsvga = (f_pxl_clk => 40000000
|
|
nfps => 60
|
|
ts_h => (ncyc_scan => 800
|
|
ncyc_porch_front => 40
|
|
ncyc_sync_pulse => 128
|
|
ncyc_porch_back => 88
|
|
sync_polarity => '0')
|
|
ts_v => (ncyc_scan => 600
|
|
ncyc_porch_front => 1
|
|
ncyc_sync_pulse => 4
|
|
ncyc_porch_back => 23
|
|
sync_polarity => '0'))
|
|
Entity <vga_timing> analyzed. Unit <vga_timing> generated.
|
|
|
|
Analyzing generic Entity <vga_sync.1> in library <work> (Architecture <Behavioral>).
|
|
ts = (ncyc_scan => 800
|
|
ncyc_porch_front => 40
|
|
ncyc_sync_pulse => 128
|
|
ncyc_porch_back => 88
|
|
sync_polarity => '0')
|
|
Entity <vga_sync.1> analyzed. Unit <vga_sync.1> generated.
|
|
|
|
Analyzing generic Entity <vga_sync.2> in library <work> (Architecture <Behavioral>).
|
|
ts = (ncyc_scan => 600
|
|
ncyc_porch_front => 1
|
|
ncyc_sync_pulse => 4
|
|
ncyc_porch_back => 23
|
|
sync_polarity => '0')
|
|
Entity <vga_sync.2> analyzed. Unit <vga_sync.2> generated.
|
|
|
|
Analyzing generic Entity <fifo_async.3> in library <work> (Architecture <Behavioral>).
|
|
addr_width = 11
|
|
allow_empty_reads = false
|
|
allow_full_writes = false
|
|
almost_empty_thresh = 256
|
|
almost_full_thresh = 1920
|
|
data_width = 64
|
|
do_last_read_update = true
|
|
Entity <fifo_async.3> analyzed. Unit <fifo_async.3> generated.
|
|
|
|
Analyzing generic Entity <fifo_async_ctrl.2> in library <work> (Architecture <Behavioral>).
|
|
addr_width = 11
|
|
almost_empty_thresh = 256
|
|
almost_full_thresh = 1920
|
|
Entity <fifo_async_ctrl.2> analyzed. Unit <fifo_async_ctrl.2> generated.
|
|
|
|
Analyzing generic Entity <gray_counter.2> in library <work> (Architecture <Behavioral>).
|
|
init_value = 0
|
|
width = 12
|
|
Entity <gray_counter.2> analyzed. Unit <gray_counter.2> generated.
|
|
|
|
Analyzing generic Entity <dpram_1w1r.4> in library <work> (Architecture <Behavioral>).
|
|
addr_width = 11
|
|
data_width = 64
|
|
Entity <dpram_1w1r.4> analyzed. Unit <dpram_1w1r.4> generated.
|
|
|
|
Analyzing generic Entity <fifo_sync.2> in library <work> (Architecture <Behavioral>).
|
|
addr_width = 9
|
|
allow_empty_reads = false
|
|
allow_full_writes = false
|
|
almost_empty_thresh = 4
|
|
almost_full_thresh = 12
|
|
data_width = 64
|
|
do_last_read_update = true
|
|
Entity <fifo_sync.2> analyzed. Unit <fifo_sync.2> generated.
|
|
|
|
Analyzing generic Entity <fifo_sync_ctrl.2> in library <work> (Architecture <Behavioral>).
|
|
addr_width = 9
|
|
almost_empty_thresh = 4
|
|
almost_full_thresh = 12
|
|
Entity <fifo_sync_ctrl.2> analyzed. Unit <fifo_sync_ctrl.2> generated.
|
|
|
|
Analyzing generic Entity <dpram_1w1r.5> in library <work> (Architecture <Behavioral>).
|
|
addr_width = 9
|
|
data_width = 64
|
|
Entity <dpram_1w1r.5> analyzed. Unit <dpram_1w1r.5> generated.
|
|
|
|
Analyzing generic Entity <fifo_sync.3> in library <work> (Architecture <Behavioral>).
|
|
addr_width = 2
|
|
allow_empty_reads = false
|
|
allow_full_writes = false
|
|
almost_empty_thresh = 4
|
|
almost_full_thresh = 12
|
|
data_width = 105
|
|
do_last_read_update = false
|
|
Entity <fifo_sync.3> analyzed. Unit <fifo_sync.3> generated.
|
|
|
|
Analyzing generic Entity <fifo_sync_ctrl.3> in library <work> (Architecture <Behavioral>).
|
|
addr_width = 2
|
|
almost_empty_thresh = 4
|
|
almost_full_thresh = 12
|
|
INFO:Xst:2679 - Register <fifo_afull> in unit <fifo_sync_ctrl.3> has a constant value of 0 during circuit operation. The register is replaced by logic.
|
|
Entity <fifo_sync_ctrl.3> analyzed. Unit <fifo_sync_ctrl.3> generated.
|
|
|
|
Analyzing generic Entity <dpram_1w1r.6> in library <work> (Architecture <Behavioral>).
|
|
addr_width = 2
|
|
data_width = 105
|
|
Entity <dpram_1w1r.6> analyzed. Unit <dpram_1w1r.6> generated.
|
|
|
|
Analyzing generic Entity <char_gen> in library <work> (Architecture <Behavioral>).
|
|
CHARACTER_SCALE = 1
|
|
CHAR_ROM_DEPTH = 256
|
|
CHAR_ROM_SIZE_X = 8
|
|
CHAR_ROM_SIZE_Y = 16
|
|
CHAR_SPACING_X = 0
|
|
CHAR_SPACING_Y = 0
|
|
MAX_CHAR_PER_LINE = 80
|
|
MAX_LINE_PER_FRAME = 32
|
|
SCREEN_OFFSET_X = 16
|
|
SCREEN_OFFSET_Y = 16
|
|
tsvga = (f_pxl_clk => 40000000
|
|
nfps => 60
|
|
ts_h => (ncyc_scan => 800
|
|
ncyc_porch_front => 40
|
|
ncyc_sync_pulse => 128
|
|
ncyc_porch_back => 88
|
|
sync_polarity => '0')
|
|
ts_v => (ncyc_scan => 600
|
|
ncyc_porch_front => 1
|
|
ncyc_sync_pulse => 4
|
|
ncyc_porch_back => 23
|
|
sync_polarity => '0'))
|
|
Entity <char_gen> analyzed. Unit <char_gen> generated.
|
|
|
|
Analyzing Entity <char_rom> in library <work> (Architecture <RTL>).
|
|
Entity <char_rom> analyzed. Unit <char_rom> generated.
|
|
|
|
Analyzing generic Entity <dpram_1w1r.7> in library <work> (Architecture <Behavioral>).
|
|
addr_width = 12
|
|
data_width = 8
|
|
Entity <dpram_1w1r.7> analyzed. Unit <dpram_1w1r.7> generated.
|
|
|
|
Analyzing generic Entity <ac97_wb> in library <work> (Architecture <behavior>).
|
|
fifo_depth = 8
|
|
Entity <ac97_wb> analyzed. Unit <ac97_wb> generated.
|
|
|
|
Analyzing generic Entity <fifo_sync.4> in library <work> (Architecture <Behavioral>).
|
|
addr_width = 8
|
|
allow_empty_reads = false
|
|
allow_full_writes = false
|
|
almost_empty_thresh = 25
|
|
almost_full_thresh = 230
|
|
data_width = 18
|
|
do_last_read_update = true
|
|
Entity <fifo_sync.4> analyzed. Unit <fifo_sync.4> generated.
|
|
|
|
Analyzing generic Entity <fifo_sync_ctrl.4> in library <work> (Architecture <Behavioral>).
|
|
addr_width = 8
|
|
almost_empty_thresh = 25
|
|
almost_full_thresh = 230
|
|
Entity <fifo_sync_ctrl.4> analyzed. Unit <fifo_sync_ctrl.4> generated.
|
|
|
|
Analyzing generic Entity <dpram_1w1r.8> in library <work> (Architecture <Behavioral>).
|
|
addr_width = 8
|
|
data_width = 18
|
|
Entity <dpram_1w1r.8> analyzed. Unit <dpram_1w1r.8> generated.
|
|
|
|
Analyzing Entity <ac_io> in library <work> (Architecture <Behavioral>).
|
|
Entity <ac_io> analyzed. Unit <ac_io> generated.
|
|
|
|
Analyzing Entity <ac_in> in library <work> (Architecture <behavioral>).
|
|
WARNING:Xst:790 - "W:/vhdl/lib/ac97_ctrl/src/core/ac_in.vhd" line 128: Index value(s) does not match array range, simulation mismatch.
|
|
Entity <ac_in> analyzed. Unit <ac_in> generated.
|
|
|
|
Analyzing generic Entity <singleshot.1> in library <work> (Architecture <behavioral>).
|
|
mode = 0
|
|
Entity <singleshot.1> analyzed. Unit <singleshot.1> generated.
|
|
|
|
Analyzing generic Entity <singleshot.2> in library <work> (Architecture <behavioral>).
|
|
mode = 1
|
|
Entity <singleshot.2> analyzed. Unit <singleshot.2> generated.
|
|
|
|
Analyzing Entity <ac_out> in library <work> (Architecture <behavioral>).
|
|
WARNING:Xst:790 - "W:/vhdl/lib/ac97_ctrl/src/core/ac_out.vhd" line 127: Index value(s) does not match array range, simulation mismatch.
|
|
WARNING:Xst:790 - "W:/vhdl/lib/ac97_ctrl/src/core/ac_out.vhd" line 128: Index value(s) does not match array range, simulation mismatch.
|
|
Entity <ac_out> analyzed. Unit <ac_out> generated.
|
|
|
|
Analyzing generic Entity <ps2_wb> in library <work> (Architecture <behavior>).
|
|
f_sys_clk = 100.000000
|
|
INFO:Xst:2679 - Register <DAT_O<31>> in unit <ps2_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
|
|
INFO:Xst:2679 - Register <DAT_O<30>> in unit <ps2_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
|
|
INFO:Xst:2679 - Register <DAT_O<29>> in unit <ps2_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
|
|
INFO:Xst:2679 - Register <DAT_O<28>> in unit <ps2_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
|
|
INFO:Xst:2679 - Register <DAT_O<27>> in unit <ps2_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
|
|
INFO:Xst:2679 - Register <DAT_O<26>> in unit <ps2_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
|
|
INFO:Xst:2679 - Register <DAT_O<25>> in unit <ps2_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
|
|
INFO:Xst:2679 - Register <DAT_O<24>> in unit <ps2_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
|
|
INFO:Xst:2679 - Register <DAT_O<23>> in unit <ps2_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
|
|
INFO:Xst:2679 - Register <DAT_O<22>> in unit <ps2_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
|
|
INFO:Xst:2679 - Register <DAT_O<21>> in unit <ps2_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
|
|
INFO:Xst:2679 - Register <DAT_O<20>> in unit <ps2_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
|
|
INFO:Xst:2679 - Register <DAT_O<19>> in unit <ps2_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
|
|
INFO:Xst:2679 - Register <DAT_O<18>> in unit <ps2_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
|
|
INFO:Xst:2679 - Register <DAT_O<17>> in unit <ps2_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
|
|
INFO:Xst:2679 - Register <DAT_O<16>> in unit <ps2_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
|
|
Entity <ps2_wb> analyzed. Unit <ps2_wb> generated.
|
|
|
|
Analyzing generic Entity <ps2_core> in library <work> (Architecture <Behavioral>).
|
|
f_sys_clk = 100.000000
|
|
WARNING:Xst:819 - "W:/vhdl/lib/ps2_port/src/ps2_core.vhd" line 191: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
|
|
<sipo_reg>
|
|
WARNING:Xst:819 - "W:/vhdl/lib/ps2_port/src/ps2_core.vhd" line 204: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
|
|
<piso_reg>
|
|
Entity <ps2_core> analyzed. Unit <ps2_core> generated.
|
|
|
|
Analyzing Entity <ps2_phy> in library <work> (Architecture <Behavioral>).
|
|
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <IOBUF_inst_ps2_clk> in unit <ps2_phy>.
|
|
Set user-defined property "DRIVE = 2" for instance <IOBUF_inst_ps2_clk> in unit <ps2_phy>.
|
|
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance <IOBUF_inst_ps2_clk> in unit <ps2_phy>.
|
|
Set user-defined property "IFD_DELAY_VALUE = AUTO" for instance <IOBUF_inst_ps2_clk> in unit <ps2_phy>.
|
|
Set user-defined property "IOSTANDARD = DEFAULT" for instance <IOBUF_inst_ps2_clk> in unit <ps2_phy>.
|
|
Set user-defined property "SLEW = SLOW" for instance <IOBUF_inst_ps2_clk> in unit <ps2_phy>.
|
|
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <IOBUF_inst_ps2_data> in unit <ps2_phy>.
|
|
Set user-defined property "DRIVE = 2" for instance <IOBUF_inst_ps2_data> in unit <ps2_phy>.
|
|
Set user-defined property "IBUF_DELAY_VALUE = 0" for instance <IOBUF_inst_ps2_data> in unit <ps2_phy>.
|
|
Set user-defined property "IFD_DELAY_VALUE = AUTO" for instance <IOBUF_inst_ps2_data> in unit <ps2_phy>.
|
|
Set user-defined property "IOSTANDARD = DEFAULT" for instance <IOBUF_inst_ps2_data> in unit <ps2_phy>.
|
|
Set user-defined property "SLEW = SLOW" for instance <IOBUF_inst_ps2_data> in unit <ps2_phy>.
|
|
Entity <ps2_phy> analyzed. Unit <ps2_phy> generated.
|
|
|
|
Analyzing generic Entity <debounce> in library <work> (Architecture <behavioral>).
|
|
ncyc_latency = 8
|
|
Entity <debounce> analyzed. Unit <debounce> generated.
|
|
|
|
|
|
=========================================================================
|
|
* HDL Synthesis *
|
|
=========================================================================
|
|
|
|
Performing bidirectional port resolution...
|
|
|
|
Synthesizing Unit <lcd_port>.
|
|
Related source file is "W:/vhdl/lib/misc/lcd_port.vhd".
|
|
WARNING:Xst:647 - Input <din<4>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
Found 4-bit tristate buffer for signal <lcd_d>.
|
|
Found 8-bit register for signal <dout>.
|
|
Found 4-bit register for signal <vlcd.d>.
|
|
Found 1-bit register for signal <vlcd.e>.
|
|
Found 1-bit register for signal <vlcd.rs>.
|
|
Found 1-bit register for signal <vlcd.rw>.
|
|
Summary:
|
|
inferred 15 D-type flip-flop(s).
|
|
inferred 4 Tristate(s).
|
|
Unit <lcd_port> synthesized.
|
|
|
|
|
|
Synthesizing Unit <gpio_wb>.
|
|
Related source file is "W:/vhdl/lib/misc/gpio_wb.vhd".
|
|
WARNING:Xst:647 - Input <ADDR_I<31:7>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <ADDR_I<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <MRDY_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:1780 - Signal <cnt_usec_preset> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
|
|
WARNING:Xst:1780 - Signal <cnt_sec_preset> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
|
|
Found 32-bit register for signal <DAT_O>.
|
|
Found 32-bit register for signal <sys_gpo0>.
|
|
Found 32-bit register for signal <sys_gpo1>.
|
|
Found 1-bit register for signal <ACK_O>.
|
|
Found 32-bit up counter for signal <cnt_sec>.
|
|
Found 1-bit register for signal <cnt_sec_en>.
|
|
Found 32-bit comparator less for signal <cnt_sec_en$cmp_lt0000> created at line 259.
|
|
Found 1-bit register for signal <cnt_sec_we>.
|
|
Found 32-bit up counter for signal <cnt_usec>.
|
|
Found 32-bit comparator greatequal for signal <cnt_usec$cmp_ge0000> created at line 259.
|
|
Found 1-bit register for signal <cnt_usec_en>.
|
|
Found 1-bit register for signal <cnt_usec_we>.
|
|
Found 32-bit register for signal <gpi0_reg>.
|
|
Found 32-bit register for signal <gpi1_reg>.
|
|
Found 32-bit register for signal <gpo0_reg>.
|
|
Found 32-bit register for signal <gpo1_reg>.
|
|
Found 32-bit register for signal <reg_data_wr>.
|
|
Found 7-bit up counter for signal <tick_usec>.
|
|
Found 7-bit comparator greatequal for signal <tick_usec$cmp_ge0000> created at line 241.
|
|
Found 64-bit register for signal <timer_cmp>.
|
|
Found 2-bit register for signal <timer_cmp_we>.
|
|
Found 32-bit up counter for signal <timer_cnt>.
|
|
Found 32-bit comparator greatequal for signal <timer_cnt_0$cmp_ge0000> created at line 296.
|
|
Found 32-bit comparator greatequal for signal <timer_cnt_1$cmp_ge0000> created at line 296.
|
|
Found 2-bit register for signal <timer_cnt_we>.
|
|
Found 2-bit register for signal <timer_en>.
|
|
Found 2-bit register for signal <timer_inten>.
|
|
Found 2-bit register for signal <timer_irq>.
|
|
Found 2-bit register for signal <timer_irq_ack>.
|
|
Found 2-bit register for signal <timer_ovl>.
|
|
Found 32-bit comparator less for signal <timer_ovl_0$cmp_lt0000> created at line 296.
|
|
Found 32-bit comparator less for signal <timer_ovl_1$cmp_lt0000> created at line 296.
|
|
Summary:
|
|
inferred 5 Counter(s).
|
|
inferred 339 D-type flip-flop(s).
|
|
inferred 7 Comparator(s).
|
|
Unit <gpio_wb> synthesized.
|
|
|
|
|
|
Synthesizing Unit <async_port_wb_1>.
|
|
Related source file is "W:/vhdl/lib/misc/async_port_wb.vhd".
|
|
WARNING:Xst:647 - Input <SEL_I<3:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <ADDR_I<31:25>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <MRDY_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:646 - Signal <page_mode_en_r> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
|
WARNING:Xst:646 - Signal <SEL_I_r<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
|
WARNING:Xst:646 - Signal <ADDR_I_r<3:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
|
INFO:Xst:1799 - State leadout is never reached in FSM <s>.
|
|
Found finite state machine <FSM_0> for signal <s>.
|
|
-----------------------------------------------------------------------
|
|
| States | 6 |
|
|
| Transitions | 14 |
|
|
| Inputs | 4 |
|
|
| Outputs | 5 |
|
|
| Clock | CLK_I (rising_edge) |
|
|
| Reset | RST_I (positive) |
|
|
| Reset type | synchronous |
|
|
| Reset State | start |
|
|
| Power Up State | start |
|
|
| Encoding | automatic |
|
|
| Implementation | LUT |
|
|
-----------------------------------------------------------------------
|
|
Found 32-bit register for signal <DAT_O>.
|
|
Found 1-bit register for signal <async_wr>.
|
|
Found 1-bit register for signal <async_rst>.
|
|
Found 25-bit register for signal <async_a>.
|
|
Found 32-bit tristate buffer for signal <async_d>.
|
|
Found 1-bit register for signal <ACK_O>.
|
|
Found 1-bit register for signal <async_be<0>>.
|
|
Found 1-bit register for signal <async_cs>.
|
|
Found 1-bit register for signal <async_rd>.
|
|
Found 25-bit register for signal <ADDR_I_r>.
|
|
Found 5-bit down counter for signal <cycle_cnt>.
|
|
Found 32-bit register for signal <DAT_I_r>.
|
|
Found 21-bit comparator equal for signal <do_page_read$cmp_eq0000> created at line 83.
|
|
Found 32-bit register for signal <Mtridata_async_d> created at line 310.
|
|
Found 1-bit register for signal <Mtrien_async_d> created at line 310.
|
|
Found 1-bit register for signal <rdyo>.
|
|
Found 1-bit register for signal <WE_I_r>.
|
|
Summary:
|
|
inferred 1 Finite State Machine(s).
|
|
inferred 1 Counter(s).
|
|
inferred 155 D-type flip-flop(s).
|
|
inferred 1 Comparator(s).
|
|
inferred 32 Tristate(s).
|
|
Unit <async_port_wb_1> synthesized.
|
|
|
|
|
|
Synthesizing Unit <async_port_wb_2>.
|
|
Related source file is "W:/vhdl/lib/misc/async_port_wb.vhd".
|
|
WARNING:Xst:647 - Input <DAT_I<31:16>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:1305 - Output <DAT_O<31:16>> is never assigned. Tied to value 0000000000000000.
|
|
WARNING:Xst:647 - Input <SEL_I<3:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <ADDR_I<31:4>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <MRDY_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:646 - Signal <page_mode_en_r> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
|
WARNING:Xst:646 - Signal <SEL_I_r<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
|
WARNING:Xst:646 - Signal <ADDR_I_r> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
|
Found finite state machine <FSM_1> for signal <s>.
|
|
-----------------------------------------------------------------------
|
|
| States | 7 |
|
|
| Transitions | 13 |
|
|
| Inputs | 2 |
|
|
| Outputs | 6 |
|
|
| Clock | CLK_I (rising_edge) |
|
|
| Reset | RST_I (positive) |
|
|
| Reset type | synchronous |
|
|
| Reset State | start |
|
|
| Power Up State | start |
|
|
| Encoding | automatic |
|
|
| Implementation | LUT |
|
|
-----------------------------------------------------------------------
|
|
Found 16-bit register for signal <DAT_O<15:0>>.
|
|
Found 1-bit register for signal <async_wr>.
|
|
Found 1-bit register for signal <async_rst>.
|
|
Found 4-bit register for signal <async_a>.
|
|
Found 16-bit tristate buffer for signal <async_d>.
|
|
Found 1-bit register for signal <ACK_O>.
|
|
Found 1-bit register for signal <async_be<0>>.
|
|
Found 1-bit register for signal <async_cs>.
|
|
Found 1-bit register for signal <async_rd>.
|
|
Found 5-bit down counter for signal <cycle_cnt>.
|
|
Found 16-bit register for signal <DAT_I_r>.
|
|
Found 16-bit register for signal <Mtridata_async_d> created at line 310.
|
|
Found 1-bit register for signal <Mtrien_async_d> created at line 310.
|
|
Found 1-bit register for signal <rdyo>.
|
|
Found 1-bit register for signal <WE_I_r>.
|
|
Summary:
|
|
inferred 1 Finite State Machine(s).
|
|
inferred 1 Counter(s).
|
|
inferred 61 D-type flip-flop(s).
|
|
inferred 16 Tristate(s).
|
|
Unit <async_port_wb_2> synthesized.
|
|
|
|
|
|
Synthesizing Unit <fifo_sync_ctrl_1>.
|
|
Related source file is "W:/vhdl/lib/FIFO/src/fifo_sync_ctrl.vhd".
|
|
WARNING:Xst:1780 - Signal <pW_cnt> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
|
|
WARNING:Xst:1780 - Signal <pR_cnt> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
|
|
Found 1-bit register for signal <fifo_aempty>.
|
|
Found 1-bit register for signal <fifo_afull>.
|
|
Found 6-bit updown counter for signal <diff>.
|
|
Found 1-bit register for signal <empty>.
|
|
Found 6-bit comparator lessequal for signal <fifo_aempty$cmp_le0000> created at line 104.
|
|
Found 6-bit comparator greatequal for signal <fifo_afull$cmp_ge0000> created at line 90.
|
|
Found 1-bit register for signal <full>.
|
|
Found 5-bit register for signal <pR>.
|
|
Found 5-bit adder for signal <pR_next$addsub0000> created at line 192.
|
|
Found 5-bit comparator equal for signal <pre_empty$cmp_eq0000> created at line 140.
|
|
Found 5-bit comparator equal for signal <pre_full$cmp_eq0000> created at line 135.
|
|
Found 5-bit register for signal <pW>.
|
|
Found 5-bit adder for signal <pW_next$addsub0000> created at line 174.
|
|
Found 1-bit register for signal <was_write>.
|
|
Summary:
|
|
inferred 1 Counter(s).
|
|
inferred 15 D-type flip-flop(s).
|
|
inferred 2 Adder/Subtractor(s).
|
|
inferred 4 Comparator(s).
|
|
Unit <fifo_sync_ctrl_1> synthesized.
|
|
|
|
|
|
Synthesizing Unit <dpram_1w1r_1>.
|
|
Related source file is "W:/vhdl/lib/misc/dpram_1w1r.vhd".
|
|
Found 32x30-bit dual-port RAM <Mram_RAM> for signal <RAM>.
|
|
Found 30-bit register for signal <dout_b>.
|
|
Summary:
|
|
inferred 1 RAM(s).
|
|
inferred 30 D-type flip-flop(s).
|
|
Unit <dpram_1w1r_1> synthesized.
|
|
|
|
|
|
Synthesizing Unit <dpram_1w1r_2>.
|
|
Related source file is "W:/vhdl/lib/misc/dpram_1w1r.vhd".
|
|
Found 32x72-bit dual-port RAM <Mram_RAM> for signal <RAM>.
|
|
Found 72-bit register for signal <dout_b>.
|
|
Summary:
|
|
inferred 1 RAM(s).
|
|
inferred 72 D-type flip-flop(s).
|
|
Unit <dpram_1w1r_2> synthesized.
|
|
|
|
|
|
Synthesizing Unit <gray_counter_1>.
|
|
Related source file is "W:/vhdl/lib/FIFO/src/gray_counter.vhd".
|
|
Found 6-bit register for signal <cntb>.
|
|
Found 6-bit register for signal <cntg>.
|
|
Found 6-bit adder for signal <nxtb$addsub0000> created at line 78.
|
|
Found 1-bit xor2 for signal <nxtg$xor0000> created at line 48.
|
|
Found 1-bit xor2 for signal <nxtg$xor0001> created at line 48.
|
|
Found 1-bit xor2 for signal <nxtg$xor0002> created at line 48.
|
|
Found 1-bit xor2 for signal <nxtg$xor0003> created at line 48.
|
|
Found 1-bit xor2 for signal <nxtg$xor0004> created at line 48.
|
|
Summary:
|
|
inferred 12 D-type flip-flop(s).
|
|
inferred 1 Adder/Subtractor(s).
|
|
Unit <gray_counter_1> synthesized.
|
|
|
|
|
|
Synthesizing Unit <dpram_1w1r_3>.
|
|
Related source file is "W:/vhdl/lib/misc/dpram_1w1r.vhd".
|
|
Found 32x64-bit dual-port RAM <Mram_RAM> for signal <RAM>.
|
|
Found 64-bit register for signal <dout_b>.
|
|
Summary:
|
|
inferred 1 RAM(s).
|
|
inferred 64 D-type flip-flop(s).
|
|
Unit <dpram_1w1r_3> synthesized.
|
|
|
|
|
|
Synthesizing Unit <sdram_ctrl>.
|
|
Related source file is "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd".
|
|
WARNING:Xst:646 - Signal <row_addr_last<10>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
|
WARNING:Xst:646 - Signal <col_addr_last> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
|
Found finite state machine <FSM_2> for signal <st_ctrl>.
|
|
-----------------------------------------------------------------------
|
|
| States | 13 |
|
|
| Transitions | 37 |
|
|
| Inputs | 12 |
|
|
| Outputs | 15 |
|
|
| Clock | clk (rising_edge) |
|
|
| Reset | rst (positive) |
|
|
| Reset type | asynchronous |
|
|
| Reset State | reset |
|
|
| Power Up State | reset |
|
|
| Encoding | automatic |
|
|
| Implementation | LUT |
|
|
-----------------------------------------------------------------------
|
|
Found 15x27-bit ROM for signal <$rom0000>.
|
|
Found 4-bit register for signal <bank_active_reg>.
|
|
Found 2-bit register for signal <bank_addr_last>.
|
|
Found 2-bit register for signal <bank_addr_reg>.
|
|
Found 1-bit 4-to-1 multiplexer for signal <bank_is_active>.
|
|
Found 9-bit register for signal <col_addr_reg>.
|
|
Found 8-bit down counter for signal <cycle_cnt>.
|
|
Found 1-bit register for signal <cycle_finished>.
|
|
Found 15-bit down counter for signal <pwr_up_cnt>.
|
|
Found 1-bit register for signal <pwr_up_finished>.
|
|
Found 10-bit down counter for signal <refresh_cnt>.
|
|
Found 1-bit register for signal <refresh_request>.
|
|
Found 13-bit register for signal <row_addr_last>.
|
|
Found 13-bit register for signal <row_addr_reg>.
|
|
Found 5-bit up counter for signal <seq_cnt>.
|
|
Found 13-bit comparator not equal for signal <st_ctrl$cmp_ne0000> created at line 264.
|
|
Found 4-bit register for signal <u_tag_reg>.
|
|
Summary:
|
|
inferred 1 Finite State Machine(s).
|
|
inferred 1 ROM(s).
|
|
inferred 4 Counter(s).
|
|
inferred 50 D-type flip-flop(s).
|
|
inferred 1 Comparator(s).
|
|
inferred 1 Multiplexer(s).
|
|
Unit <sdram_ctrl> synthesized.
|
|
|
|
|
|
Synthesizing Unit <sdram_cmd>.
|
|
Related source file is "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd".
|
|
INFO:Xst:1799 - State write_a is never reached in FSM <st_sdr>.
|
|
INFO:Xst:1799 - State read_a is never reached in FSM <st_sdr>.
|
|
INFO:Xst:1799 - State burst_stop is never reached in FSM <st_sdr>.
|
|
INFO:Xst:1799 - State self_ref is never reached in FSM <st_sdr>.
|
|
INFO:Xst:1799 - State pre_pwr_down is never reached in FSM <st_sdr>.
|
|
INFO:Xst:1799 - State act_pwr_down is never reached in FSM <st_sdr>.
|
|
Found finite state machine <FSM_3> for signal <st_sdr>.
|
|
-----------------------------------------------------------------------
|
|
| States | 8 |
|
|
| Transitions | 28 |
|
|
| Inputs | 10 |
|
|
| Outputs | 5 |
|
|
| Clock | clk (rising_edge) |
|
|
| Reset | rst (positive) |
|
|
| Reset type | asynchronous |
|
|
| Reset State | pwr_down |
|
|
| Power Up State | pwr_down |
|
|
| Encoding | automatic |
|
|
| Implementation | LUT |
|
|
-----------------------------------------------------------------------
|
|
Found 10x4-bit ROM for signal <$mux0000> created at line 98.
|
|
Found 2-bit register for signal <burst_cnt>.
|
|
Found 2-bit subtractor for signal <burst_cnt$addsub0000> created at line 281.
|
|
Found 1-bit register for signal <burst_finished>.
|
|
Found 4-bit down counter for signal <cycle_cnt>.
|
|
Found 1-bit register for signal <cycle_finished>.
|
|
Summary:
|
|
inferred 1 Finite State Machine(s).
|
|
inferred 1 ROM(s).
|
|
inferred 1 Counter(s).
|
|
inferred 4 D-type flip-flop(s).
|
|
inferred 1 Adder/Subtractor(s).
|
|
Unit <sdram_cmd> synthesized.
|
|
|
|
|
|
Synthesizing Unit <dpram_1w1r_9>.
|
|
Related source file is "W:/vhdl/lib/misc/dpram_1w1r.vhd".
|
|
Found 32x32-bit dual-port RAM <Mram_RAM> for signal <RAM>.
|
|
Found 32-bit register for signal <dout_b>.
|
|
Summary:
|
|
inferred 1 RAM(s).
|
|
inferred 32 D-type flip-flop(s).
|
|
Unit <dpram_1w1r_9> synthesized.
|
|
|
|
|
|
Synthesizing Unit <vga_sync_1>.
|
|
Related source file is "W:/vhdl/lib/VGA_ctrl/src/vga_sync.vhd".
|
|
Found finite state machine <FSM_4> for signal <state>.
|
|
-----------------------------------------------------------------------
|
|
| States | 5 |
|
|
| Transitions | 9 |
|
|
| Inputs | 4 |
|
|
| Outputs | 5 |
|
|
| Clock | clk (rising_edge) |
|
|
| Clock enable | ce (positive) |
|
|
| Reset | rst (positive) |
|
|
| Reset type | asynchronous |
|
|
| Reset State | st_init |
|
|
| Power Up State | st_init |
|
|
| Encoding | automatic |
|
|
| Implementation | LUT |
|
|
-----------------------------------------------------------------------
|
|
Found 10-bit up counter for signal <count>.
|
|
Summary:
|
|
inferred 1 Finite State Machine(s).
|
|
inferred 1 Counter(s).
|
|
Unit <vga_sync_1> synthesized.
|
|
|
|
|
|
Synthesizing Unit <vga_sync_2>.
|
|
Related source file is "W:/vhdl/lib/VGA_ctrl/src/vga_sync.vhd".
|
|
Found finite state machine <FSM_5> for signal <state>.
|
|
-----------------------------------------------------------------------
|
|
| States | 5 |
|
|
| Transitions | 9 |
|
|
| Inputs | 4 |
|
|
| Outputs | 5 |
|
|
| Clock | clk (rising_edge) |
|
|
| Clock enable | ce (positive) |
|
|
| Reset | rst (positive) |
|
|
| Reset type | asynchronous |
|
|
| Reset State | st_init |
|
|
| Power Up State | st_init |
|
|
| Encoding | automatic |
|
|
| Implementation | LUT |
|
|
-----------------------------------------------------------------------
|
|
Found 10-bit up counter for signal <count>.
|
|
Summary:
|
|
inferred 1 Finite State Machine(s).
|
|
inferred 1 Counter(s).
|
|
Unit <vga_sync_2> synthesized.
|
|
|
|
|
|
Synthesizing Unit <dpram_1w1r_4>.
|
|
Related source file is "W:/vhdl/lib/misc/dpram_1w1r.vhd".
|
|
Found 2048x64-bit dual-port RAM <Mram_RAM> for signal <RAM>.
|
|
Found 64-bit register for signal <dout_b>.
|
|
Summary:
|
|
inferred 1 RAM(s).
|
|
inferred 64 D-type flip-flop(s).
|
|
Unit <dpram_1w1r_4> synthesized.
|
|
|
|
|
|
Synthesizing Unit <gray_counter_2>.
|
|
Related source file is "W:/vhdl/lib/FIFO/src/gray_counter.vhd".
|
|
Found 12-bit register for signal <cntb>.
|
|
Found 12-bit register for signal <cntg>.
|
|
Found 12-bit adder for signal <nxtb$addsub0000> created at line 78.
|
|
Found 1-bit xor2 for signal <nxtg$xor0000> created at line 48.
|
|
Found 1-bit xor2 for signal <nxtg$xor0001> created at line 48.
|
|
Found 1-bit xor2 for signal <nxtg$xor0002> created at line 48.
|
|
Found 1-bit xor2 for signal <nxtg$xor0003> created at line 48.
|
|
Found 1-bit xor2 for signal <nxtg$xor0004> created at line 48.
|
|
Found 1-bit xor2 for signal <nxtg$xor0005> created at line 48.
|
|
Found 1-bit xor2 for signal <nxtg$xor0006> created at line 48.
|
|
Found 1-bit xor2 for signal <nxtg$xor0007> created at line 48.
|
|
Found 1-bit xor2 for signal <nxtg$xor0008> created at line 48.
|
|
Found 1-bit xor2 for signal <nxtg$xor0009> created at line 48.
|
|
Found 1-bit xor2 for signal <nxtg$xor0010> created at line 48.
|
|
Summary:
|
|
inferred 24 D-type flip-flop(s).
|
|
inferred 1 Adder/Subtractor(s).
|
|
Unit <gray_counter_2> synthesized.
|
|
|
|
|
|
Synthesizing Unit <fifo_sync_ctrl_2>.
|
|
Related source file is "W:/vhdl/lib/FIFO/src/fifo_sync_ctrl.vhd".
|
|
WARNING:Xst:1780 - Signal <pW_cnt> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
|
|
WARNING:Xst:1780 - Signal <pR_cnt> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
|
|
Found 1-bit register for signal <fifo_aempty>.
|
|
Found 1-bit register for signal <fifo_afull>.
|
|
Found 10-bit updown counter for signal <diff>.
|
|
Found 1-bit register for signal <empty>.
|
|
Found 10-bit comparator lessequal for signal <fifo_aempty$cmp_le0000> created at line 104.
|
|
Found 10-bit comparator greatequal for signal <fifo_afull$cmp_ge0000> created at line 90.
|
|
Found 1-bit register for signal <full>.
|
|
Found 9-bit register for signal <pR>.
|
|
Found 9-bit adder for signal <pR_next$addsub0000> created at line 192.
|
|
Found 9-bit comparator equal for signal <pre_empty$cmp_eq0000> created at line 140.
|
|
Found 9-bit comparator equal for signal <pre_full$cmp_eq0000> created at line 135.
|
|
Found 9-bit register for signal <pW>.
|
|
Found 9-bit adder for signal <pW_next$addsub0000> created at line 174.
|
|
Found 1-bit register for signal <was_write>.
|
|
Summary:
|
|
inferred 1 Counter(s).
|
|
inferred 23 D-type flip-flop(s).
|
|
inferred 2 Adder/Subtractor(s).
|
|
inferred 4 Comparator(s).
|
|
Unit <fifo_sync_ctrl_2> synthesized.
|
|
|
|
|
|
Synthesizing Unit <dpram_1w1r_5>.
|
|
Related source file is "W:/vhdl/lib/misc/dpram_1w1r.vhd".
|
|
Found 512x64-bit dual-port RAM <Mram_RAM> for signal <RAM>.
|
|
Found 64-bit register for signal <dout_b>.
|
|
Summary:
|
|
inferred 1 RAM(s).
|
|
inferred 64 D-type flip-flop(s).
|
|
Unit <dpram_1w1r_5> synthesized.
|
|
|
|
|
|
Synthesizing Unit <fifo_sync_ctrl_3>.
|
|
Related source file is "W:/vhdl/lib/FIFO/src/fifo_sync_ctrl.vhd".
|
|
WARNING:Xst:1780 - Signal <pW_cnt> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
|
|
WARNING:Xst:1780 - Signal <pR_cnt> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
|
|
Found 1-bit register for signal <fifo_aempty>.
|
|
Found 3-bit updown counter for signal <diff>.
|
|
Found 1-bit register for signal <empty>.
|
|
Found 3-bit comparator lessequal for signal <fifo_aempty$cmp_le0000> created at line 104.
|
|
Found 1-bit register for signal <full>.
|
|
Found 2-bit register for signal <pR>.
|
|
Found 2-bit adder for signal <pR_next$addsub0000> created at line 192.
|
|
Found 2-bit comparator equal for signal <pre_empty$cmp_eq0000> created at line 140.
|
|
Found 2-bit comparator equal for signal <pre_full$cmp_eq0000> created at line 135.
|
|
Found 2-bit register for signal <pW>.
|
|
Found 2-bit adder for signal <pW_next$addsub0000> created at line 174.
|
|
Found 1-bit register for signal <was_write>.
|
|
Summary:
|
|
inferred 1 Counter(s).
|
|
inferred 8 D-type flip-flop(s).
|
|
inferred 2 Adder/Subtractor(s).
|
|
inferred 3 Comparator(s).
|
|
Unit <fifo_sync_ctrl_3> synthesized.
|
|
|
|
|
|
Synthesizing Unit <dpram_1w1r_6>.
|
|
Related source file is "W:/vhdl/lib/misc/dpram_1w1r.vhd".
|
|
Found 4x105-bit dual-port RAM <Mram_RAM> for signal <RAM>.
|
|
Found 105-bit register for signal <dout_b>.
|
|
Summary:
|
|
inferred 1 RAM(s).
|
|
inferred 105 D-type flip-flop(s).
|
|
Unit <dpram_1w1r_6> synthesized.
|
|
|
|
|
|
Synthesizing Unit <char_rom>.
|
|
Related source file is "W:/vhdl/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x16.vhd".
|
|
Found 4096x8-bit ROM for signal <DATA$rom0000> created at line 4378.
|
|
Found 8-bit register for signal <DATA>.
|
|
Summary:
|
|
inferred 1 ROM(s).
|
|
inferred 8 D-type flip-flop(s).
|
|
Unit <char_rom> synthesized.
|
|
|
|
|
|
Synthesizing Unit <dpram_1w1r_7>.
|
|
Related source file is "W:/vhdl/lib/misc/dpram_1w1r.vhd".
|
|
Found 4096x8-bit dual-port RAM <Mram_RAM> for signal <RAM>.
|
|
Found 8-bit register for signal <dout_b>.
|
|
Summary:
|
|
inferred 1 RAM(s).
|
|
inferred 8 D-type flip-flop(s).
|
|
Unit <dpram_1w1r_7> synthesized.
|
|
|
|
|
|
Synthesizing Unit <fifo_sync_ctrl_4>.
|
|
Related source file is "W:/vhdl/lib/FIFO/src/fifo_sync_ctrl.vhd".
|
|
WARNING:Xst:1780 - Signal <pW_cnt> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
|
|
WARNING:Xst:1780 - Signal <pR_cnt> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
|
|
Found 1-bit register for signal <fifo_aempty>.
|
|
Found 1-bit register for signal <fifo_afull>.
|
|
Found 9-bit updown counter for signal <diff>.
|
|
Found 1-bit register for signal <empty>.
|
|
Found 9-bit comparator lessequal for signal <fifo_aempty$cmp_le0000> created at line 104.
|
|
Found 9-bit comparator greatequal for signal <fifo_afull$cmp_ge0000> created at line 90.
|
|
Found 1-bit register for signal <full>.
|
|
Found 8-bit register for signal <pR>.
|
|
Found 8-bit adder for signal <pR_next$addsub0000> created at line 192.
|
|
Found 8-bit comparator equal for signal <pre_empty$cmp_eq0000> created at line 140.
|
|
Found 8-bit comparator equal for signal <pre_full$cmp_eq0000> created at line 135.
|
|
Found 8-bit register for signal <pW>.
|
|
Found 8-bit adder for signal <pW_next$addsub0000> created at line 174.
|
|
Found 1-bit register for signal <was_write>.
|
|
Summary:
|
|
inferred 1 Counter(s).
|
|
inferred 21 D-type flip-flop(s).
|
|
inferred 2 Adder/Subtractor(s).
|
|
inferred 4 Comparator(s).
|
|
Unit <fifo_sync_ctrl_4> synthesized.
|
|
|
|
|
|
Synthesizing Unit <dpram_1w1r_8>.
|
|
Related source file is "W:/vhdl/lib/misc/dpram_1w1r.vhd".
|
|
Found 256x18-bit dual-port RAM <Mram_RAM> for signal <RAM>.
|
|
Found 18-bit register for signal <dout_b>.
|
|
Summary:
|
|
inferred 1 RAM(s).
|
|
inferred 18 D-type flip-flop(s).
|
|
Unit <dpram_1w1r_8> synthesized.
|
|
|
|
|
|
Synthesizing Unit <singleshot_1>.
|
|
Related source file is "W:/vhdl/lib/misc/singleshot.vhd".
|
|
Found finite state machine <FSM_6> for signal <s>.
|
|
-----------------------------------------------------------------------
|
|
| States | 4 |
|
|
| Transitions | 6 |
|
|
| Inputs | 1 |
|
|
| Outputs | 1 |
|
|
| Clock | clk (rising_edge) |
|
|
| Reset | rst (positive) |
|
|
| Reset type | synchronous |
|
|
| Reset State | idle |
|
|
| Power Up State | idle |
|
|
| Encoding | automatic |
|
|
| Implementation | LUT |
|
|
-----------------------------------------------------------------------
|
|
Summary:
|
|
inferred 1 Finite State Machine(s).
|
|
Unit <singleshot_1> synthesized.
|
|
|
|
|
|
Synthesizing Unit <singleshot_2>.
|
|
Related source file is "W:/vhdl/lib/misc/singleshot.vhd".
|
|
Found finite state machine <FSM_7> for signal <s>.
|
|
-----------------------------------------------------------------------
|
|
| States | 4 |
|
|
| Transitions | 6 |
|
|
| Inputs | 1 |
|
|
| Outputs | 1 |
|
|
| Clock | clk (rising_edge) |
|
|
| Reset | rst (positive) |
|
|
| Reset type | synchronous |
|
|
| Reset State | idle |
|
|
| Power Up State | idle |
|
|
| Encoding | automatic |
|
|
| Implementation | LUT |
|
|
-----------------------------------------------------------------------
|
|
Summary:
|
|
inferred 1 Finite State Machine(s).
|
|
Unit <singleshot_2> synthesized.
|
|
|
|
|
|
Synthesizing Unit <ps2_core>.
|
|
Related source file is "W:/vhdl/lib/ps2_port/src/ps2_core.vhd".
|
|
WARNING:Xst:646 - Signal <tx_rdy> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
|
WARNING:Xst:1780 - Signal <rx_err> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
|
|
INFO:Xst:1799 - State tx_start_latency_st is never reached in FSM <write_cs>.
|
|
INFO:Xst:1799 - State tx_stop_sample_st is never reached in FSM <write_cs>.
|
|
Found finite state machine <FSM_8> for signal <write_cs>.
|
|
-----------------------------------------------------------------------
|
|
| States | 18 |
|
|
| Transitions | 41 |
|
|
| Inputs | 5 |
|
|
| Outputs | 30 |
|
|
| Clock | clk (rising_edge) |
|
|
| Reset | rst (positive) |
|
|
| Reset type | synchronous |
|
|
| Reset State | tx_idle_st |
|
|
| Power Up State | tx_idle_st |
|
|
| Encoding | automatic |
|
|
| Implementation | LUT |
|
|
-----------------------------------------------------------------------
|
|
Found finite state machine <FSM_9> for signal <read_cs>.
|
|
-----------------------------------------------------------------------
|
|
| States | 14 |
|
|
| Transitions | 38 |
|
|
| Inputs | 6 |
|
|
| Outputs | 8 |
|
|
| Clock | clk (rising_edge) |
|
|
| Reset | rst (positive) |
|
|
| Reset type | synchronous |
|
|
| Reset State | start_wait_st |
|
|
| Power Up State | start_wait_st |
|
|
| Encoding | automatic |
|
|
| Implementation | LUT |
|
|
-----------------------------------------------------------------------
|
|
Found 1-bit register for signal <rx_err_flag>.
|
|
Found 1-bit register for signal <tx_empty>.
|
|
Found 1-bit register for signal <ps2_data_tx>.
|
|
Found 1-bit register for signal <rx_err_par>.
|
|
Found 1-bit register for signal <ps2_clk_tx>.
|
|
Found 8-bit register for signal <dout>.
|
|
Found 7-bit down counter for signal <cnt_prescaler>.
|
|
Found 3-bit down counter for signal <data_cnt>.
|
|
Found 3-bit down counter for signal <data_cnt_tx>.
|
|
Found 1-bit register for signal <en_us>.
|
|
Found 1-bit register for signal <parity_rx>.
|
|
Found 1-bit register for signal <parity_tx>.
|
|
Found 8-bit register for signal <piso_reg>.
|
|
Found 1-bit register for signal <rx_full>.
|
|
Found 8-bit register for signal <sipo_reg>.
|
|
Found 14-bit down counter for signal <timeout_count_rx>.
|
|
Found 14-bit down counter for signal <timeout_count_tx>.
|
|
Found 1-bit register for signal <timeout_rx_flag>.
|
|
Found 1-bit register for signal <timeout_tx_flag>.
|
|
Found 8-bit register for signal <tx_reg>.
|
|
Found 1-bit register for signal <tx_req>.
|
|
Summary:
|
|
inferred 2 Finite State Machine(s).
|
|
inferred 5 Counter(s).
|
|
inferred 44 D-type flip-flop(s).
|
|
Unit <ps2_core> synthesized.
|
|
|
|
|
|
Synthesizing Unit <debounce>.
|
|
Related source file is "W:/vhdl/lib/ps2_port/src/debounce.vhd".
|
|
Found finite state machine <FSM_10> for signal <debounce_cs>.
|
|
-----------------------------------------------------------------------
|
|
| States | 3 |
|
|
| Transitions | 7 |
|
|
| Inputs | 3 |
|
|
| Outputs | 2 |
|
|
| Clock | clk (rising_edge) |
|
|
| Clock enable | rst (negative) |
|
|
| Power Up State | init_st |
|
|
| Encoding | automatic |
|
|
| Implementation | LUT |
|
|
-----------------------------------------------------------------------
|
|
Found 1-bit register for signal <output>.
|
|
Found 3-bit register for signal <count>.
|
|
Found 3-bit subtractor for signal <count$addsub0000> created at line 59.
|
|
Found 1-bit register for signal <input_last>.
|
|
Summary:
|
|
inferred 1 Finite State Machine(s).
|
|
inferred 5 D-type flip-flop(s).
|
|
inferred 1 Adder/Subtractor(s).
|
|
Unit <debounce> synthesized.
|
|
|
|
|
|
Synthesizing Unit <clockgen>.
|
|
Related source file is "W:/vhdl/projects/mips_sys/src/clockgen_virtex4.vhd".
|
|
Found 1-bit register for signal <sys_rst_out>.
|
|
Found 5-bit down counter for signal <reset_cnt>.
|
|
Found 20-bit register for signal <reset_pipe0>.
|
|
Found 20-bit register for signal <reset_pipe1>.
|
|
Found 20-bit register for signal <reset_pipe2>.
|
|
Summary:
|
|
inferred 1 Counter(s).
|
|
inferred 61 D-type flip-flop(s).
|
|
Unit <clockgen> synthesized.
|
|
|
|
|
|
Synthesizing Unit <ps2_wb>.
|
|
Related source file is "W:/vhdl/lib/ps2_port/src/ps2_wb.vhd".
|
|
WARNING:Xst:647 - Input <DAT_I<31:8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <SEL_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <ADDR_I<31:6>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <ADDR_I<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <MRDY_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
Found 16-bit register for signal <DAT_O<15:0>>.
|
|
Found 1-bit register for signal <ACK_O>.
|
|
Found 1-bit register for signal <INT_O>.
|
|
Found 1-bit register for signal <irq_rx>.
|
|
Found 1-bit register for signal <irq_tx>.
|
|
Found 8-bit register for signal <reg_ps2_tx>.
|
|
Found 1-bit register for signal <reg_re_ps2_rx>.
|
|
Found 1-bit register for signal <reg_we_ps2_tx>.
|
|
Found 1-bit register for signal <rx_int_en>.
|
|
Found 1-bit register for signal <stat_clk>.
|
|
Found 1-bit register for signal <stat_data>.
|
|
Found 1-bit register for signal <tx_int_en>.
|
|
Summary:
|
|
inferred 34 D-type flip-flop(s).
|
|
Unit <ps2_wb> synthesized.
|
|
|
|
|
|
Synthesizing Unit <ps2_phy>.
|
|
Related source file is "W:/vhdl/lib/ps2_port/src/ps2_phy_virtex.vhd".
|
|
Unit <ps2_phy> synthesized.
|
|
|
|
|
|
Synthesizing Unit <rom>.
|
|
Related source file is "W:/vhdl/projects/mips_sys/src/bootloader.ROM_ld.vhd".
|
|
WARNING:Xst:647 - Input <addr<31:13>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <addr<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:646 - Signal <jtag_ld_addr<15:11>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
|
WARNING:Xst:646 - Signal <bs_capture> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
|
Found 2048x32-bit dual-port RAM <Mram_word_array> for signal <word_array>.
|
|
Found 32-bit register for signal <dout>.
|
|
Found 32-bit register for signal <jtag_ld_dout>.
|
|
Found 48-bit register for signal <user_regi>.
|
|
Found 48-bit register for signal <user_rego>.
|
|
Summary:
|
|
inferred 1 RAM(s).
|
|
inferred 160 D-type flip-flop(s).
|
|
Unit <rom> synthesized.
|
|
|
|
|
|
Synthesizing Unit <kcuart_tx>.
|
|
Related source file is "W:/vhdl/lib/uart/kcuart_tx.vhd".
|
|
Unit <kcuart_tx> synthesized.
|
|
|
|
|
|
Synthesizing Unit <bbfifo_16x8>.
|
|
Related source file is "W:/vhdl/lib/uart/bbfifo_16x8.vhd".
|
|
Unit <bbfifo_16x8> synthesized.
|
|
|
|
|
|
Synthesizing Unit <kcuart_rx>.
|
|
Related source file is "W:/vhdl/lib/uart/kcuart_rx.vhd".
|
|
Unit <kcuart_rx> synthesized.
|
|
|
|
|
|
Synthesizing Unit <fifo_sync_1>.
|
|
Related source file is "W:/vhdl/lib/FIFO/src/fifo_sync.vhd".
|
|
WARNING:Xst:646 - Signal <pre_full> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
|
WARNING:Xst:646 - Signal <pre_empty> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
|
Unit <fifo_sync_1> synthesized.
|
|
|
|
|
|
Synthesizing Unit <fifo_async_ctrl_1>.
|
|
Related source file is "W:/vhdl/lib/FIFO/src/fifo_async_ctrl.vhd".
|
|
Found 1-bit register for signal <fifo_aempty>.
|
|
Found 1-bit register for signal <fifo_afull>.
|
|
Found 6-bit register for signal <bcnt2_ar>.
|
|
Found 6-bit register for signal <bcnt2_aw>.
|
|
Found 6-bit register for signal <diff>.
|
|
Found 6-bit adder for signal <diff$addsub0000>.
|
|
Found 6-bit subtractor for signal <diff$sub0000> created at line 189.
|
|
Found 6-bit register for signal <diff0>.
|
|
Found 6-bit adder for signal <diff0$addsub0000>.
|
|
Found 6-bit subtractor for signal <diff0$sub0000> created at line 209.
|
|
Found 1-bit register for signal <empty>.
|
|
Found 6-bit comparator lessequal for signal <fifo_aempty$cmp_le0000> created at line 204.
|
|
Found 6-bit comparator greatequal for signal <fifo_afull$cmp_ge0000> created at line 184.
|
|
Found 1-bit register for signal <full>.
|
|
Found 6-bit register for signal <gcnt2_r>.
|
|
Found 6-bit register for signal <gcnt2_w>.
|
|
Found 6-bit register for signal <p1>.
|
|
Found 6-bit register for signal <p10>.
|
|
Found 6-bit register for signal <p11>.
|
|
Found 6-bit register for signal <p12>.
|
|
Found 6-bit register for signal <p2>.
|
|
Found 6-bit register for signal <p20>.
|
|
Found 6-bit register for signal <p21>.
|
|
Found 6-bit register for signal <p22>.
|
|
Found 6-bit comparator equal for signal <pre_empty$cmp_eq0000> created at line 144.
|
|
Found 6-bit comparator equal for signal <pre_full$cmp_eq0000> created at line 134.
|
|
Summary:
|
|
inferred 88 D-type flip-flop(s).
|
|
inferred 4 Adder/Subtractor(s).
|
|
inferred 4 Comparator(s).
|
|
Unit <fifo_async_ctrl_1> synthesized.
|
|
|
|
|
|
Synthesizing Unit <ddr_phy>.
|
|
Related source file is "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd".
|
|
Found 4-bit register for signal <u_tag_wr>.
|
|
Found 13-bit register for signal <part_addr>.
|
|
Found 1-bit register for signal <part_we_n>.
|
|
Found 1-bit register for signal <part_ras_n>.
|
|
Found 4-bit tristate buffer for signal <part_dqs>.
|
|
Found 2-bit register for signal <part_ba>.
|
|
Found 1-bit register for signal <part_cas_n>.
|
|
Found 1-bit register for signal <sdr_data_req_w>.
|
|
Found 64-bit register for signal <sdr_data_r>.
|
|
Found 4-bit register for signal <u_tag_rd>.
|
|
Found 32-bit tristate buffer for signal <part_data>.
|
|
Found 1-bit register for signal <sdr_data_vld>.
|
|
Found 1-bit register for signal <part_cke>.
|
|
Found 1-bit register for signal <part_cs_n>.
|
|
Found 64-bit register for signal <data_reg_r>.
|
|
Found 1-bit register for signal <dqs_rst>.
|
|
Found 4-bit register for signal <dqs_zen>.
|
|
Found 1-bit register for signal <drive>.
|
|
Found 32-bit register for signal <drive270>.
|
|
Found 2-bit register for signal <p>.
|
|
Found 4-bit register for signal <p0>.
|
|
Found 13-bit register for signal <part_ctrl_reg.addr>.
|
|
Found 2-bit register for signal <part_ctrl_reg.ba>.
|
|
Found 1-bit register for signal <part_ctrl_reg.cke>.
|
|
Found 1-bit register for signal <part_ctrl_reg.cmd.cas_n>.
|
|
Found 1-bit register for signal <part_ctrl_reg.cmd.cs_n>.
|
|
Found 1-bit register for signal <part_ctrl_reg.cmd.ras_n>.
|
|
Found 1-bit register for signal <part_ctrl_reg.cmd.we_n>.
|
|
Found 1-bit register for signal <read_en>.
|
|
Found 20-bit register for signal <u_tag_pipe>.
|
|
Found 1-bit register for signal <we_reg>.
|
|
Summary:
|
|
inferred 244 D-type flip-flop(s).
|
|
inferred 36 Tristate(s).
|
|
Unit <ddr_phy> synthesized.
|
|
|
|
|
|
Synthesizing Unit <fifo_sync_2>.
|
|
Related source file is "W:/vhdl/lib/FIFO/src/fifo_sync.vhd".
|
|
WARNING:Xst:646 - Signal <pre_full> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
|
WARNING:Xst:646 - Signal <pre_empty> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
|
Unit <fifo_sync_2> synthesized.
|
|
|
|
|
|
Synthesizing Unit <fifo_sync_3>.
|
|
Related source file is "W:/vhdl/lib/FIFO/src/fifo_sync.vhd".
|
|
WARNING:Xst:646 - Signal <pre_full> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
|
Unit <fifo_sync_3> synthesized.
|
|
|
|
|
|
Synthesizing Unit <char_gen>.
|
|
Related source file is "W:/vhdl/lib/VGA_ctrl/src/char_gen.vhd".
|
|
Found 32x12-bit ROM for signal <a_addr_rd$rom0000> created at line 99.
|
|
Found 32x8-bit ROM for signal <cursor_rom_data$rom0000> created at line 451.
|
|
Found 32x12-bit ROM for signal <line_addr$rom0000> created at line 99.
|
|
Found finite state machine <FSM_11> for signal <s>.
|
|
-----------------------------------------------------------------------
|
|
| States | 4 |
|
|
| Transitions | 8 |
|
|
| Inputs | 4 |
|
|
| Outputs | 5 |
|
|
| Clock | sys_clk (rising_edge) |
|
|
| Reset | rst (positive) |
|
|
| Reset type | synchronous |
|
|
| Reset State | cg_init |
|
|
| Power Up State | cg_init |
|
|
| Encoding | automatic |
|
|
| Implementation | LUT |
|
|
-----------------------------------------------------------------------
|
|
Found 1-bit register for signal <char_draw_en>.
|
|
Found 8-bit register for signal <dout>.
|
|
Found 12-bit adder for signal <a_addr_rd>.
|
|
Found 12-bit adder for signal <a_addr_wr$addsub0000> created at line 267.
|
|
Found 12-bit adder for signal <a_addr_wr$addsub0001> created at line 245.
|
|
Found 12-bit up counter for signal <a_cnt>.
|
|
Found 12-bit comparator greatequal for signal <a_cnt$cmp_ge0000> created at line 304.
|
|
Found 8-bit register for signal <a_data_reg>.
|
|
Found 8-bit comparator less for signal <a_data_reg$cmp_lt0000> created at line 330.
|
|
Found 8-bit subtractor for signal <a_data_reg$sub0000> created at line 338.
|
|
Found 1-bit register for signal <a_data_we>.
|
|
Found 7-bit up counter for signal <cell_x_cnt>.
|
|
Found 7-bit comparator greatequal for signal <cell_x_cnt$cmp_ge0000> created at line 518.
|
|
Found 5-bit register for signal <cell_y_cnt>.
|
|
Found 5-bit adder for signal <cell_y_cnt$addsub0000> created at line 527.
|
|
Found 5-bit comparator greatequal for signal <cell_y_cnt$cmp_ge0000> created at line 526.
|
|
Found 4-bit comparator greatequal for signal <cell_y_cnt$cmp_ge0001> created at line 522.
|
|
Found 3-bit comparator greatequal for signal <cell_y_cnt$cmp_ge0002> created at line 514.
|
|
Found 5-bit comparator less for signal <cell_y_cnt$cmp_lt0000> created at line 526.
|
|
Found 1-bit register for signal <char_en>.
|
|
Found 1-bit register for signal <char_en2>.
|
|
Found 8-bit register for signal <char_reg>.
|
|
Found 1-bit xor2 for signal <char_reg_0$xor0000> created at line 473.
|
|
Found 1-bit xor2 for signal <char_reg_1$xor0000> created at line 473.
|
|
Found 1-bit xor2 for signal <char_reg_2$xor0000> created at line 473.
|
|
Found 1-bit xor2 for signal <char_reg_3$xor0000> created at line 473.
|
|
Found 1-bit xor2 for signal <char_reg_4$xor0000> created at line 473.
|
|
Found 1-bit xor2 for signal <char_reg_5$xor0000> created at line 473.
|
|
Found 1-bit xor2 for signal <char_reg_6$xor0000> created at line 473.
|
|
Found 1-bit xor2 for signal <char_reg_7$xor0000> created at line 473.
|
|
Found 4-bit register for signal <char_rom_row>.
|
|
Found 3-bit register for signal <char_x_cnt>.
|
|
Found 3-bit adder for signal <char_x_cnt$addsub0000> created at line 515.
|
|
Found 3-bit comparator less for signal <char_x_cnt$cmp_lt0000> created at line 514.
|
|
Found 4-bit up counter for signal <char_y_cnt>.
|
|
Found 4-bit comparator less for signal <char_y_cnt$cmp_lt0000> created at line 522.
|
|
Found 7-bit comparator less for signal <char_y_cnt$cmp_lt0001> created at line 518.
|
|
Found 7-bit register for signal <csr_posx_cnt_din>.
|
|
Found 1-bit register for signal <csr_posx_cnt_en>.
|
|
Found 1-bit register for signal <csr_posx_cnt_set>.
|
|
Found 1-bit register for signal <csr_posx_overflow>.
|
|
Found 7-bit comparator less for signal <csr_posx_overflow$cmp_lt0000> created at line 356.
|
|
Found 7-bit up counter for signal <csr_posx_reg>.
|
|
Found 7-bit comparator greatequal for signal <csr_posx_reg$cmp_ge0000> created at line 356.
|
|
Found 7-bit register for signal <csr_posx_synced>.
|
|
Found 5-bit register for signal <csr_posy_cnt_din>.
|
|
Found 1-bit register for signal <csr_posy_cnt_en>.
|
|
Found 8-bit comparator greatequal for signal <csr_posy_cnt_en$cmp_ge0000> created at line 330.
|
|
Found 1-bit register for signal <csr_posy_cnt_set>.
|
|
Found 1-bit register for signal <csr_posy_overflow>.
|
|
Found 5-bit comparator less for signal <csr_posy_overflow$cmp_lt0000> created at line 376.
|
|
Found 5-bit up counter for signal <csr_posy_reg>.
|
|
Found 5-bit comparator greatequal for signal <csr_posy_reg$cmp_ge0000> created at line 376.
|
|
Found 5-bit register for signal <csr_posy_synced>.
|
|
Found 5-bit up counter for signal <cursor_cnt>.
|
|
Found 8-bit register for signal <cursor_rom_data>.
|
|
Found 7-bit comparator equal for signal <cursor_rom_data$cmp_eq0000> created at line 450.
|
|
Found 5-bit comparator equal for signal <cursor_rom_data$cmp_eq0001> created at line 450.
|
|
Found 1-bit register for signal <cursor_visible>.
|
|
Found 5-bit comparator less for signal <cursor_visible$cmp_lt0000> created at line 436.
|
|
Found 1-bit register for signal <enable_x>.
|
|
Found 1-bit register for signal <enable_y>.
|
|
Found 5-bit register for signal <line_offset>.
|
|
Found 5-bit adder for signal <line_offset$addsub0000> created at line 532.
|
|
Found 5-bit comparator less for signal <line_offset$cmp_lt0000> created at line 531.
|
|
Found 7-bit register for signal <p1>.
|
|
Found 5-bit register for signal <p10>.
|
|
Found 7-bit register for signal <p2>.
|
|
Found 5-bit register for signal <p20>.
|
|
Found 1-bit register for signal <scroll_active>.
|
|
Found 5-bit register for signal <scroll_offset>.
|
|
Found 5-bit adder for signal <scroll_offset$addsub0000> created at line 399.
|
|
Summary:
|
|
inferred 1 Finite State Machine(s).
|
|
inferred 3 ROM(s).
|
|
inferred 6 Counter(s).
|
|
inferred 116 D-type flip-flop(s).
|
|
inferred 8 Adder/Subtractor(s).
|
|
inferred 19 Comparator(s).
|
|
Unit <char_gen> synthesized.
|
|
|
|
|
|
Synthesizing Unit <vga_timing>.
|
|
Related source file is "W:/vhdl/lib/VGA_ctrl/src/vga_timing.vhd".
|
|
Unit <vga_timing> synthesized.
|
|
|
|
|
|
Synthesizing Unit <fifo_async_ctrl_2>.
|
|
Related source file is "W:/vhdl/lib/FIFO/src/fifo_async_ctrl.vhd".
|
|
Found 1-bit register for signal <fifo_aempty>.
|
|
Found 1-bit register for signal <fifo_afull>.
|
|
Found 12-bit register for signal <bcnt2_ar>.
|
|
Found 12-bit register for signal <bcnt2_aw>.
|
|
Found 12-bit register for signal <diff>.
|
|
Found 12-bit adder for signal <diff$addsub0000>.
|
|
Found 12-bit subtractor for signal <diff$sub0000> created at line 189.
|
|
Found 12-bit register for signal <diff0>.
|
|
Found 12-bit adder for signal <diff0$addsub0000>.
|
|
Found 12-bit subtractor for signal <diff0$sub0000> created at line 209.
|
|
Found 1-bit register for signal <empty>.
|
|
Found 12-bit comparator lessequal for signal <fifo_aempty$cmp_le0000> created at line 204.
|
|
Found 12-bit comparator greatequal for signal <fifo_afull$cmp_ge0000> created at line 184.
|
|
Found 1-bit register for signal <full>.
|
|
Found 12-bit register for signal <gcnt2_r>.
|
|
Found 12-bit register for signal <gcnt2_w>.
|
|
Found 12-bit register for signal <p1>.
|
|
Found 12-bit register for signal <p10>.
|
|
Found 12-bit register for signal <p11>.
|
|
Found 12-bit register for signal <p12>.
|
|
Found 12-bit register for signal <p2>.
|
|
Found 12-bit register for signal <p20>.
|
|
Found 12-bit register for signal <p21>.
|
|
Found 12-bit register for signal <p22>.
|
|
Found 12-bit comparator equal for signal <pre_empty$cmp_eq0000> created at line 144.
|
|
Found 12-bit comparator equal for signal <pre_full$cmp_eq0000> created at line 134.
|
|
Summary:
|
|
inferred 172 D-type flip-flop(s).
|
|
inferred 4 Adder/Subtractor(s).
|
|
inferred 4 Comparator(s).
|
|
Unit <fifo_async_ctrl_2> synthesized.
|
|
|
|
|
|
Synthesizing Unit <fifo_sync_4>.
|
|
Related source file is "W:/vhdl/lib/FIFO/src/fifo_sync.vhd".
|
|
WARNING:Xst:646 - Signal <pre_full> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
|
WARNING:Xst:646 - Signal <pre_empty> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
|
Unit <fifo_sync_4> synthesized.
|
|
|
|
|
|
Synthesizing Unit <ac_in>.
|
|
Related source file is "W:/vhdl/lib/ac97_ctrl/src/core/ac_in.vhd".
|
|
WARNING:Xst:646 - Signal <tag<2:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
|
WARNING:Xst:646 - Signal <last_slot> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
|
Found finite state machine <FSM_12> for signal <sac>.
|
|
-----------------------------------------------------------------------
|
|
| States | 3 |
|
|
| Transitions | 9 |
|
|
| Inputs | 5 |
|
|
| Outputs | 3 |
|
|
| Clock | ac_bit_clk (rising_edge) |
|
|
| Reset | ac_reset (positive) |
|
|
| Reset type | asynchronous |
|
|
| Reset State | ac_idle |
|
|
| Power Up State | ac_idle |
|
|
| Encoding | automatic |
|
|
| Implementation | LUT |
|
|
-----------------------------------------------------------------------
|
|
Found 13-bit register for signal <slot_valid>.
|
|
Found 1-bit register for signal <sync_status>.
|
|
Found 20-bit register for signal <stat_data>.
|
|
Found 20-bit register for signal <stat_addr>.
|
|
Found 5-bit up counter for signal <bitcnt>.
|
|
Found 240-bit register for signal <data_array>.
|
|
Found 4-bit comparator greater for signal <pcm_out_data$cmp_gt0000> created at line 127.
|
|
Found 20-bit register for signal <rx_reg>.
|
|
Found 4-bit up counter for signal <slotcnt>.
|
|
Found 1-bit register for signal <stat_read>.
|
|
Found 16-bit register for signal <tag>.
|
|
Summary:
|
|
inferred 1 Finite State Machine(s).
|
|
inferred 2 Counter(s).
|
|
inferred 331 D-type flip-flop(s).
|
|
inferred 1 Comparator(s).
|
|
Unit <ac_in> synthesized.
|
|
|
|
|
|
Synthesizing Unit <ac_out>.
|
|
Related source file is "W:/vhdl/lib/ac97_ctrl/src/core/ac_out.vhd".
|
|
Found finite state machine <FSM_13> for signal <sac>.
|
|
-----------------------------------------------------------------------
|
|
| States | 3 |
|
|
| Transitions | 6 |
|
|
| Inputs | 3 |
|
|
| Outputs | 3 |
|
|
| Clock | ac_bit_clk (rising_edge) |
|
|
| Reset | ac_reset (positive) |
|
|
| Reset type | asynchronous |
|
|
| Reset State | ac_idle |
|
|
| Power Up State | ac_idle |
|
|
| Encoding | automatic |
|
|
| Implementation | LUT |
|
|
-----------------------------------------------------------------------
|
|
Found 1-bit register for signal <ac_ssync>.
|
|
Found 1-bit register for signal <ac_sdata_out>.
|
|
Found 5-bit up counter for signal <bitcnt>.
|
|
Found 240-bit register for signal <data_array>.
|
|
Found 1-bit register for signal <last_slot>.
|
|
Found 12-bit register for signal <slot_valid>.
|
|
Found 4-bit up counter for signal <slotcnt>.
|
|
Found 20-bit register for signal <tx_reg>.
|
|
Summary:
|
|
inferred 1 Finite State Machine(s).
|
|
inferred 2 Counter(s).
|
|
inferred 275 D-type flip-flop(s).
|
|
Unit <ac_out> synthesized.
|
|
|
|
|
|
Synthesizing Unit <rom_wb>.
|
|
Related source file is "W:/vhdl/lib/misc/rom_wb.vhd".
|
|
Found 1-bit register for signal <ACK_O>.
|
|
Summary:
|
|
inferred 1 D-type flip-flop(s).
|
|
Unit <rom_wb> synthesized.
|
|
|
|
|
|
Synthesizing Unit <uart_tx>.
|
|
Related source file is "W:/vhdl/lib/uart/uart_tx.vhd".
|
|
Unit <uart_tx> synthesized.
|
|
|
|
|
|
Synthesizing Unit <uart_rx>.
|
|
Related source file is "W:/vhdl/lib/uart/uart_rx.vhd".
|
|
Unit <uart_rx> synthesized.
|
|
|
|
|
|
Synthesizing Unit <fifo_async_1>.
|
|
Related source file is "W:/vhdl/lib/FIFO/src/fifo_async.vhd".
|
|
WARNING:Xst:646 - Signal <pre_full> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
|
WARNING:Xst:646 - Signal <pre_empty> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
|
Unit <fifo_async_1> synthesized.
|
|
|
|
|
|
Synthesizing Unit <fifo_async_2>.
|
|
Related source file is "W:/vhdl/lib/FIFO/src/fifo_async.vhd".
|
|
WARNING:Xst:646 - Signal <pre_full> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
|
WARNING:Xst:646 - Signal <pre_empty> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
|
Unit <fifo_async_2> synthesized.
|
|
|
|
|
|
Synthesizing Unit <fifo_async_4>.
|
|
Related source file is "W:/vhdl/lib/FIFO/src/fifo_async.vhd".
|
|
WARNING:Xst:646 - Signal <pre_full> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
|
WARNING:Xst:646 - Signal <pre_empty> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
|
Unit <fifo_async_4> synthesized.
|
|
|
|
|
|
Synthesizing Unit <vga_backend>.
|
|
Related source file is "W:/vhdl/lib/VGA_ctrl/src/vga_backend.vhd".
|
|
WARNING:Xst:647 - Input <color_op> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <color_in<0><3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <color_in<1><3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <sys_clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
Found 8-bit register for signal <vga_blue>.
|
|
Found 1-bit register for signal <vga_hsync>.
|
|
Found 8-bit register for signal <vga_red>.
|
|
Found 1-bit register for signal <vga_vsync>.
|
|
Found 8-bit register for signal <vga_green>.
|
|
Found 1-bit register for signal <hsync_r>.
|
|
Found 1-bit register for signal <scan_enable>.
|
|
Found 1-bit register for signal <vsync_r>.
|
|
Summary:
|
|
inferred 29 D-type flip-flop(s).
|
|
Unit <vga_backend> synthesized.
|
|
|
|
|
|
Synthesizing Unit <fifo_async_3>.
|
|
Related source file is "W:/vhdl/lib/FIFO/src/fifo_async.vhd".
|
|
WARNING:Xst:646 - Signal <pre_full> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
|
WARNING:Xst:646 - Signal <pre_empty> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
|
Unit <fifo_async_3> synthesized.
|
|
|
|
|
|
Synthesizing Unit <ac_io>.
|
|
Related source file is "W:/vhdl/lib/ac97_ctrl/src/core/ac_io.vhd".
|
|
Found 1-bit register for signal <ac_reset_n>.
|
|
Found 1-bit register for signal <ac_reset>.
|
|
Found 10-bit down counter for signal <cnt>.
|
|
Found 10-bit subtractor for signal <cnt$addsub0000> created at line 165.
|
|
Found 1-bit register for signal <rstate<0>>.
|
|
Summary:
|
|
inferred 1 Counter(s).
|
|
inferred 3 D-type flip-flop(s).
|
|
inferred 1 Adder/Subtractor(s).
|
|
Unit <ac_io> synthesized.
|
|
|
|
|
|
Synthesizing Unit <uart_wb>.
|
|
Related source file is "W:/vhdl/lib/uart/uart_wb.vhd".
|
|
WARNING:Xst:647 - Input <DAT_I<31:16>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <SEL_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <ADDR_I<31:6>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <ADDR_I<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <MRDY_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:646 - Signal <tx_complete> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
|
Found 16-bit register for signal <DAT_O<15:0>>.
|
|
Found 1-bit register for signal <ACK_O>.
|
|
Found 16-bit up counter for signal <baud_count>.
|
|
Found 16-bit comparator equal for signal <baud_count$cmp_eq0000> created at line 162.
|
|
Found 1-bit register for signal <en_16_x_baud>.
|
|
Found 1-bit register for signal <irq_rx>.
|
|
Found 1-bit register for signal <irq_tx>.
|
|
Found 1-bit register for signal <reg_re_uart_rx>.
|
|
Found 16-bit register for signal <reg_uart_baud>.
|
|
Found 8-bit register for signal <reg_uart_tx>.
|
|
Found 1-bit register for signal <reg_we_uart_tx>.
|
|
Found 1-bit register for signal <rx_int_en>.
|
|
Found 1-bit register for signal <tx_int_en>.
|
|
Summary:
|
|
inferred 1 Counter(s).
|
|
inferred 48 D-type flip-flop(s).
|
|
inferred 1 Comparator(s).
|
|
Unit <uart_wb> synthesized.
|
|
|
|
|
|
Synthesizing Unit <vga_frontend64>.
|
|
Related source file is "W:/vhdl/lib/VGA_ctrl/src/vga_frontend64.vhd".
|
|
WARNING:Xst:647 - Input <SEL_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <ADDR_I<31:7>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <ADDR_I<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <MRDY_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:646 - Signal <stat_vsync> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
|
WARNING:Xst:646 - Signal <stat_vscan> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
|
WARNING:Xst:646 - Signal <stat_hsync> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
|
WARNING:Xst:646 - Signal <stat_hscan> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
|
WARNING:Xst:646 - Signal <odd_pixel<9:1>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
|
WARNING:Xst:646 - Signal <blitfifo_full> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
|
WARNING:Xst:653 - Signal <back> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
|
|
Found finite state machine <FSM_14> for signal <s>.
|
|
-----------------------------------------------------------------------
|
|
| States | 8 |
|
|
| Transitions | 22 |
|
|
| Inputs | 10 |
|
|
| Outputs | 9 |
|
|
| Clock | CLK_I (rising_edge) |
|
|
| Reset | RST_I (positive) |
|
|
| Reset type | synchronous |
|
|
| Reset State | init |
|
|
| Power Up State | init |
|
|
| Encoding | automatic |
|
|
| Implementation | LUT |
|
|
-----------------------------------------------------------------------
|
|
Found 1-bit register for signal <ACK_O>.
|
|
Found 1-bit register for signal <INT_O>.
|
|
Found 32-bit register for signal <SDAT_O>.
|
|
Found 32-bit adder for signal <ADDR_O_blit_dst>.
|
|
Found 32-bit adder for signal <ADDR_O_blit_src>.
|
|
Found 32-bit adder for signal <ADDR_O_scan>.
|
|
Found 32-bit register for signal <blit_addr_dst>.
|
|
Found 32-bit register for signal <blit_addr_src_0>.
|
|
Found 32-bit register for signal <blit_addr_src_1>.
|
|
Found 9-bit down counter for signal <blit_chunk_cnt>.
|
|
Found 4-bit register for signal <blit_comb_sel>.
|
|
Found 1-bit register for signal <blit_complete>.
|
|
Found 1-bit register for signal <blit_complete_ack>.
|
|
Found 1-bit register for signal <blit_complete_inten>.
|
|
Found 32-bit register for signal <blit_dimx_dst>.
|
|
Found 32-bit register for signal <blit_dimx_src_0>.
|
|
Found 32-bit register for signal <blit_dimx_src_1>.
|
|
Found 32-bit register for signal <blit_dst_cnt_x>.
|
|
Found 32-bit adder for signal <blit_dst_cnt_x$addsub0000> created at line 640.
|
|
Found 32-bit comparator equal for signal <blit_dst_cnt_x$cmp_eq0000> created at line 639.
|
|
Found 32-bit comparator not equal for signal <blit_dst_cnt_x$cmp_ne0000> created at line 639.
|
|
Found 32-bit up counter for signal <blit_dst_cnt_y>.
|
|
Found 1-bit register for signal <blit_dst_finish>.
|
|
Found 32-bit comparator not equal for signal <blit_dst_finish$cmp_ne0000> created at line 643.
|
|
Found 32-bit up accumulator for signal <blit_dst_off_y>.
|
|
Found 32-bit comparator equal for signal <blit_dst_off_y$cmp_eq0000> created at line 643.
|
|
Found 32-bit register for signal <blit_dst_offset>.
|
|
Found 32-bit adder for signal <blit_dst_offset$addsub0000> created at line 641.
|
|
Found 4-bit register for signal <blit_func_sel>.
|
|
Found 32-bit register for signal <blit_nx>.
|
|
Found 32-bit register for signal <blit_ny>.
|
|
Found 1-bit register for signal <blit_request>.
|
|
Found 1-bit register for signal <blit_request_set>.
|
|
Found 32-bit register for signal <blit_src_cnt_x>.
|
|
Found 32-bit adder for signal <blit_src_cnt_x$addsub0000> created at line 610.
|
|
Found 32-bit comparator equal for signal <blit_src_cnt_x$cmp_eq0000> created at line 609.
|
|
Found 32-bit comparator not equal for signal <blit_src_cnt_x$cmp_ne0000> created at line 609.
|
|
Found 32-bit up counter for signal <blit_src_cnt_y>.
|
|
Found 1-bit register for signal <blit_src_finish>.
|
|
Found 32-bit comparator not equal for signal <blit_src_finish$cmp_ne0000> created at line 613.
|
|
Found 32-bit up accumulator for signal <blit_src_off_y>.
|
|
Found 32-bit comparator equal for signal <blit_src_off_y$cmp_eq0000> created at line 613.
|
|
Found 32-bit register for signal <blit_src_offset>.
|
|
Found 32-bit adder for signal <blit_src_offset$addsub0000> created at line 611.
|
|
Found 1-bit register for signal <bufchg>.
|
|
Found 1-bit register for signal <bufchg_flag>.
|
|
Found 1-bit register for signal <bufchg_flag_ack>.
|
|
Found 1-bit register for signal <bufchg_irq_en>.
|
|
Found 1-bit register for signal <bus_read_fin>.
|
|
Found 29-bit comparator equal for signal <bus_read_fin$cmp_eq0000> created at line 550.
|
|
Found 1-bit register for signal <cg_ascii_we>.
|
|
Found 1-bit register for signal <cg_clr_line>.
|
|
Found 1-bit register for signal <cg_clr_screen>.
|
|
Found 32-bit register for signal <cg_color>.
|
|
Found 8-bit register for signal <cg_din>.
|
|
Found 1-bit register for signal <cg_posx_we>.
|
|
Found 1-bit register for signal <cg_posy_we>.
|
|
Found 32-bit register for signal <front>.
|
|
Found 32-bit register for signal <host_blit_nx>.
|
|
Found 32-bit register for signal <host_fb_back>.
|
|
Found 32-bit register for signal <host_fb_front>.
|
|
Found 18-bit up counter for signal <pixel_cnt>.
|
|
Found 29-bit up counter for signal <read_cnt>.
|
|
Found 29-bit up counter for signal <request_cnt>.
|
|
Found 32-bit register for signal <vga_fb_back>.
|
|
Found 32-bit register for signal <vga_fb_front>.
|
|
Found 1-bit register for signal <vga_scan_dma_en>.
|
|
Found 1-bit register for signal <vga_scan_dma_en2>.
|
|
Summary:
|
|
inferred 1 Finite State Machine(s).
|
|
inferred 6 Counter(s).
|
|
inferred 2 Accumulator(s).
|
|
inferred 677 D-type flip-flop(s).
|
|
inferred 7 Adder/Subtractor(s).
|
|
inferred 9 Comparator(s).
|
|
Unit <vga_frontend64> synthesized.
|
|
|
|
|
|
Synthesizing Unit <ac97_wb>.
|
|
Related source file is "W:/vhdl/lib/ac97_ctrl/src/core/ac97_wb.vhd".
|
|
WARNING:Xst:647 - Input <MRDY_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:646 - Signal <tx_fifo_almost_empty> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
|
WARNING:Xst:1780 - Signal <rx_state_n> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
|
|
WARNING:Xst:1780 - Signal <rx_state> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
|
|
WARNING:Xst:1780 - Signal <rx_fifo_rst> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
|
|
WARNING:Xst:646 - Signal <request<5:12>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
|
WARNING:Xst:646 - Signal <data_reg<31:18>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
|
WARNING:Xst:646 - Signal <addr_reg<31:10>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
|
WARNING:Xst:646 - Signal <addr_reg<1:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
|
WARNING:Xst:646 - Signal <ac_stat_data<3:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
|
WARNING:Xst:646 - Signal <ac_stat_addr<19:12>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
|
WARNING:Xst:646 - Signal <ac_stat_addr<1:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
|
WARNING:Xst:646 - Signal <ac_slot_valid<5:12>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
|
WARNING:Xst:646 - Signal <ac_rx_pcm_data<1:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
|
Found 32-bit register for signal <DAT_O>.
|
|
Found 1-bit register for signal <ACK_O>.
|
|
Found 20-bit register for signal <ac_cmd_addr>.
|
|
Found 20-bit register for signal <ac_cmd_data>.
|
|
Found 1-bit register for signal <ac_cmd_we>.
|
|
Found 4-bit up counter for signal <ac_tx_pcm_addr>.
|
|
Found 32-bit register for signal <addr_reg>.
|
|
Found 32-bit 4-to-1 multiplexer for signal <addr_reg$mux0000> created at line 296.
|
|
Found 1-bit register for signal <cmd_pending>.
|
|
Found 1-bit register for signal <cmd_reg_we>.
|
|
Found 32-bit 4-to-1 multiplexer for signal <DAT_O$mux0000> created at line 296.
|
|
Found 32-bit register for signal <data_reg>.
|
|
Found 32-bit 4-to-1 multiplexer for signal <data_reg$mux0000> created at line 296.
|
|
Found 1-bit register for signal <int_en_frame_sync>.
|
|
Found 1-bit register for signal <int_en_rx>.
|
|
Found 1-bit register for signal <int_en_tx>.
|
|
Found 1-bit register for signal <rx_data_ack>.
|
|
Found 1-bit register for signal <rx_data_irq>.
|
|
Found 1-bit register for signal <rx_en>.
|
|
Found 1-bit register for signal <stat_pending>.
|
|
Found 16-bit register for signal <stat_reg>.
|
|
Found 1-bit register for signal <stat_reg_re>.
|
|
Found 1-bit register for signal <stat_valid>.
|
|
Found 1-bit register for signal <tx_data_start>.
|
|
Found 1-bit register for signal <tx_en>.
|
|
Found 1-bit register for signal <tx_fifo_we>.
|
|
Summary:
|
|
inferred 1 Counter(s).
|
|
inferred 168 D-type flip-flop(s).
|
|
inferred 96 Multiplexer(s).
|
|
Unit <ac97_wb> synthesized.
|
|
|
|
|
|
Synthesizing Unit <sdram_ctrl_top>.
|
|
Related source file is "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd".
|
|
Unit <sdram_ctrl_top> synthesized.
|
|
|
|
|
|
Synthesizing Unit <sdram_ctrl_frontend64_wb>.
|
|
Related source file is "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd".
|
|
WARNING:Xst:647 - Input <ADDR_I<31:26>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:647 - Input <ADDR_I<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
|
WARNING:Xst:646 - Signal <u_tag_wr<3:1>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
|
WARNING:Xst:646 - Signal <u_tag_rd<3:1>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
|
Unit <sdram_ctrl_frontend64_wb> synthesized.
|
|
|
|
|
|
Synthesizing Unit <mips_sys>.
|
|
Related source file is "W:/vhdl/projects/mips_sys/src/mips_sys.vhd".
|
|
WARNING:Xst:646 - Signal <usb_addr<1:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
|
WARNING:Xst:646 - Signal <gpo1<31:3>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
|
WARNING:Xst:646 - Signal <gpo0<31:9>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
|
WARNING:Xst:653 - Signal <gpi1<31:8>> is used but never assigned. This sourceless signal will be automatically connected to value 000000000000000000000000.
|
|
WARNING:Xst:653 - Signal <gpi0<31:5>> is used but never assigned. This sourceless signal will be automatically connected to value 000000000000000000000000000.
|
|
WARNING:Xst:646 - Signal <flash_addr<1:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
|
Using one-hot encoding for signal <mem_area>.
|
|
Found 32-bit 4-to-1 multiplexer for signal <ADDR_O>.
|
|
Found 2-bit register for signal <arb_gnt>.
|
|
Found 1-bit register for signal <arb_idx<0>>.
|
|
Found 6-bit register for signal <INT>.
|
|
Found 64-bit 4-to-1 multiplexer for signal <MDAT_O>.
|
|
Summary:
|
|
inferred 9 D-type flip-flop(s).
|
|
inferred 96 Multiplexer(s).
|
|
Unit <mips_sys> synthesized.
|
|
|
|
|
|
=========================================================================
|
|
HDL Synthesis Report
|
|
|
|
Macro Statistics
|
|
# RAMs : 10
|
|
2048x32-bit dual-port RAM : 1
|
|
2048x64-bit dual-port RAM : 1
|
|
256x18-bit dual-port RAM : 1
|
|
32x30-bit dual-port RAM : 1
|
|
32x32-bit dual-port RAM : 1
|
|
32x64-bit dual-port RAM : 1
|
|
32x72-bit dual-port RAM : 1
|
|
4096x8-bit dual-port RAM : 1
|
|
4x105-bit dual-port RAM : 1
|
|
512x64-bit dual-port RAM : 1
|
|
# ROMs : 6
|
|
10x4-bit ROM : 1
|
|
15x27-bit ROM : 1
|
|
32x12-bit ROM : 2
|
|
32x8-bit ROM : 1
|
|
4096x8-bit ROM : 1
|
|
# Adders/Subtractors : 53
|
|
10-bit subtractor : 1
|
|
12-bit adder : 7
|
|
12-bit subtractor : 2
|
|
2-bit adder : 2
|
|
2-bit subtractor : 1
|
|
3-bit adder : 1
|
|
3-bit subtractor : 4
|
|
32-bit adder : 7
|
|
5-bit adder : 5
|
|
6-bit adder : 12
|
|
6-bit subtractor : 6
|
|
8-bit adder : 2
|
|
8-bit subtractor : 1
|
|
9-bit adder : 2
|
|
# Counters : 49
|
|
10-bit down counter : 2
|
|
10-bit up counter : 2
|
|
10-bit updown counter : 1
|
|
12-bit up counter : 1
|
|
14-bit down counter : 4
|
|
15-bit down counter : 1
|
|
16-bit up counter : 2
|
|
18-bit up counter : 1
|
|
29-bit up counter : 2
|
|
3-bit down counter : 4
|
|
3-bit updown counter : 1
|
|
32-bit up counter : 6
|
|
4-bit down counter : 1
|
|
4-bit up counter : 4
|
|
5-bit down counter : 3
|
|
5-bit up counter : 5
|
|
6-bit updown counter : 1
|
|
7-bit down counter : 2
|
|
7-bit up counter : 3
|
|
8-bit down counter : 1
|
|
9-bit down counter : 1
|
|
9-bit updown counter : 1
|
|
# Accumulators : 2
|
|
32-bit up loadable accumulator : 2
|
|
# Registers : 731
|
|
1-bit register : 493
|
|
105-bit register : 1
|
|
12-bit register : 18
|
|
13-bit register : 5
|
|
16-bit register : 6
|
|
18-bit register : 1
|
|
2-bit register : 10
|
|
20-bit register : 33
|
|
25-bit register : 2
|
|
3-bit register : 5
|
|
30-bit register : 1
|
|
32-bit register : 34
|
|
4-bit register : 15
|
|
48-bit register : 2
|
|
5-bit register : 9
|
|
6-bit register : 55
|
|
64-bit register : 5
|
|
7-bit register : 4
|
|
72-bit register : 1
|
|
8-bit register : 28
|
|
9-bit register : 3
|
|
# Comparators : 71
|
|
10-bit comparator greatequal : 1
|
|
10-bit comparator lessequal : 1
|
|
12-bit comparator equal : 2
|
|
12-bit comparator greatequal : 2
|
|
12-bit comparator lessequal : 1
|
|
13-bit comparator not equal : 1
|
|
16-bit comparator equal : 2
|
|
2-bit comparator equal : 2
|
|
21-bit comparator equal : 1
|
|
29-bit comparator equal : 1
|
|
3-bit comparator greatequal : 1
|
|
3-bit comparator less : 1
|
|
3-bit comparator lessequal : 1
|
|
32-bit comparator equal : 4
|
|
32-bit comparator greatequal : 3
|
|
32-bit comparator less : 3
|
|
32-bit comparator not equal : 4
|
|
4-bit comparator greatequal : 1
|
|
4-bit comparator greater : 1
|
|
4-bit comparator less : 1
|
|
5-bit comparator equal : 3
|
|
5-bit comparator greatequal : 2
|
|
5-bit comparator less : 4
|
|
6-bit comparator equal : 6
|
|
6-bit comparator greatequal : 4
|
|
6-bit comparator lessequal : 4
|
|
7-bit comparator equal : 1
|
|
7-bit comparator greatequal : 3
|
|
7-bit comparator less : 2
|
|
8-bit comparator equal : 2
|
|
8-bit comparator greatequal : 1
|
|
8-bit comparator less : 1
|
|
9-bit comparator equal : 2
|
|
9-bit comparator greatequal : 1
|
|
9-bit comparator lessequal : 1
|
|
# Multiplexers : 6
|
|
1-bit 4-to-1 multiplexer : 1
|
|
32-bit 4-to-1 multiplexer : 4
|
|
64-bit 4-to-1 multiplexer : 1
|
|
# Tristates : 39
|
|
1-bit tristate buffer : 36
|
|
16-bit tristate buffer : 1
|
|
32-bit tristate buffer : 1
|
|
4-bit tristate buffer : 1
|
|
# Xors : 60
|
|
1-bit xor2 : 60
|
|
|
|
=========================================================================
|
|
|
|
=========================================================================
|
|
* Advanced HDL Synthesis *
|
|
=========================================================================
|
|
|
|
Analyzing FSM <FSM_14> for best encoding.
|
|
Optimizing FSM <inst_vga_frontend/s/FSM> on signal <s[1:8]> with one-hot encoding.
|
|
----------------------------------
|
|
State | Encoding
|
|
----------------------------------
|
|
init | 00000001
|
|
rdy | 00000010
|
|
scan_bus_request | 00000100
|
|
scan_bus_read | 00100000
|
|
blit_src_bus_request | 00001000
|
|
blit_src_bus_read | 01000000
|
|
blit_dst_bus_request | 00010000
|
|
blit_dst_bus_fin | 10000000
|
|
----------------------------------
|
|
Analyzing FSM <FSM_13> for best encoding.
|
|
Optimizing FSM <inst_ac97_wb/inst_ac_io/inst_ac_out/sac/FSM> on signal <sac[1:2]> with sequential encoding.
|
|
---------------------
|
|
State | Encoding
|
|
---------------------
|
|
ac_idle | 00
|
|
ac_tag | 01
|
|
ac_data | 10
|
|
---------------------
|
|
Analyzing FSM <FSM_12> for best encoding.
|
|
Optimizing FSM <inst_ac97_wb/inst_ac_io/inst_ac_in/sac/FSM> on signal <sac[1:2]> with sequential encoding.
|
|
---------------------
|
|
State | Encoding
|
|
---------------------
|
|
ac_idle | 00
|
|
ac_tag | 01
|
|
ac_data | 10
|
|
---------------------
|
|
Analyzing FSM <FSM_11> for best encoding.
|
|
Optimizing FSM <inst_vga_frontend/inst_char_gen/s/FSM> on signal <s[1:2]> with gray encoding.
|
|
---------------------------
|
|
State | Encoding
|
|
---------------------------
|
|
cg_init | 00
|
|
cg_ready | 10
|
|
cg_clr_line | 11
|
|
cg_clr_screen | 01
|
|
---------------------------
|
|
Analyzing FSM <FSM_9> for best encoding.
|
|
Optimizing FSM <inst_ps2_wb_0/inst_ps2_core/read_cs/FSM> on signal <read_cs[1:4]> with gray encoding.
|
|
Optimizing FSM <inst_ps2_wb_1/inst_ps2_core/read_cs/FSM> on signal <read_cs[1:4]> with gray encoding.
|
|
------------------------------
|
|
State | Encoding
|
|
------------------------------
|
|
start_wait_st | 0000
|
|
start_trans_st | 0001
|
|
start_sample_st | 0011
|
|
data_wait_st | 0010
|
|
data_trans_st | 0110
|
|
data_sample_st | 0111
|
|
parity_wait_st | 0101
|
|
parity_trans_st | 0100
|
|
parity_sample_st | 1100
|
|
stop_wait_st | 1111
|
|
stop_trans_st | 1110
|
|
stop_sample_st | 1010
|
|
valid_st | 1011
|
|
abort_st | 1101
|
|
------------------------------
|
|
Analyzing FSM <FSM_8> for best encoding.
|
|
Optimizing FSM <inst_ps2_wb_0/inst_ps2_core/write_cs/FSM> on signal <write_cs[1:18]> with one-hot encoding.
|
|
Optimizing FSM <inst_ps2_wb_1/inst_ps2_core/write_cs/FSM> on signal <write_cs[1:18]> with one-hot encoding.
|
|
-------------------------------------------
|
|
State | Encoding
|
|
-------------------------------------------
|
|
tx_idle_st | 000000000000000001
|
|
tx_clock_assert_st | 000000000000000010
|
|
tx_start_latency_st | unreached
|
|
tx_start_assert_st | 000000000000000100
|
|
tx_clock_release_st | 000000000000001000
|
|
tx_dev_trans_st | 000000000000100000
|
|
tx_data_wait_st | 000000000001000000
|
|
tx_data_trans_st | 000000001000000000
|
|
tx_data_sample_st | 000000000010000000
|
|
tx_parity_update_st | 000000000100000000
|
|
tx_dev_wait_st | 000000000000010000
|
|
tx_parity_wait_st | 000000100000000000
|
|
tx_parity_trans_st | 000000010000000000
|
|
tx_parity_sample_st | 000001000000000000
|
|
tx_stop_wait_st | 000100000000000000
|
|
tx_stop_trans_st | 000010000000000000
|
|
tx_stop_sample_st | unreached
|
|
tx_ack_trans_st | 001000000000000000
|
|
tx_ack_sample_st | 010000000000000000
|
|
tx_valid_st | 100000000000000000
|
|
-------------------------------------------
|
|
Analyzing FSM <FSM_7> for best encoding.
|
|
Optimizing FSM <inst_ac97_wb/inst_ac_io/inst_ac_in/singleshot_inst2/s/FSM> on signal <s[1:2]> with gray encoding.
|
|
----------------------
|
|
State | Encoding
|
|
----------------------
|
|
idle | 00
|
|
shot_in | 01
|
|
active | 11
|
|
shot_out | 10
|
|
----------------------
|
|
Analyzing FSM <FSM_6> for best encoding.
|
|
Optimizing FSM <inst_ac97_wb/inst_ac_io/inst_ac_in/singleshot_inst1/s/FSM> on signal <s[1:2]> with gray encoding.
|
|
Optimizing FSM <inst_ac97_wb/inst_ac_io/inst_ac_out/singleshot_inst1/s/FSM> on signal <s[1:2]> with gray encoding.
|
|
----------------------
|
|
State | Encoding
|
|
----------------------
|
|
idle | 00
|
|
shot_in | 01
|
|
active | 11
|
|
shot_out | 10
|
|
----------------------
|
|
Analyzing FSM <FSM_5> for best encoding.
|
|
Optimizing FSM <inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_v/state/FSM> on signal <state[1:3]> with sequential encoding.
|
|
----------------------
|
|
State | Encoding
|
|
----------------------
|
|
st_init | 000
|
|
st_scan | 100
|
|
st_front | 001
|
|
st_sync | 010
|
|
st_back | 011
|
|
----------------------
|
|
Analyzing FSM <FSM_4> for best encoding.
|
|
Optimizing FSM <inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/state/FSM> on signal <state[1:3]> with sequential encoding.
|
|
----------------------
|
|
State | Encoding
|
|
----------------------
|
|
st_init | 000
|
|
st_scan | 100
|
|
st_front | 001
|
|
st_sync | 010
|
|
st_back | 011
|
|
----------------------
|
|
Analyzing FSM <FSM_3> for best encoding.
|
|
Optimizing FSM <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr/FSM> on signal <st_sdr[1:8]> with one-hot encoding.
|
|
--------------------------
|
|
State | Encoding
|
|
--------------------------
|
|
pwr_down | 00000001
|
|
precharge | 00000100
|
|
mode | 00001000
|
|
idle | 00000010
|
|
row_act | 00010000
|
|
write | 10000000
|
|
write_a | unreached
|
|
read | 01000000
|
|
read_a | unreached
|
|
burst_stop | unreached
|
|
self_ref | unreached
|
|
auto_ref | 00100000
|
|
pre_pwr_down | unreached
|
|
act_pwr_down | unreached
|
|
--------------------------
|
|
Analyzing FSM <FSM_2> for best encoding.
|
|
Optimizing FSM <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl/FSM> on signal <st_ctrl[1:13]> with one-hot encoding.
|
|
---------------------------------
|
|
State | Encoding
|
|
---------------------------------
|
|
reset | 0000000000001
|
|
power_wait | 0000000000010
|
|
init | 0000000000100
|
|
init_wait | 0000000010000
|
|
user_ready | 0000000001000
|
|
user_write_pre | 0000001000000
|
|
user_write_act | 0000010000000
|
|
user_write | 0000100000000
|
|
user_read_pre | 0001000000000
|
|
user_read_act | 0010000000000
|
|
user_read | 0100000000000
|
|
refresh_pre | 0000000100000
|
|
refresh | 1000000000000
|
|
---------------------------------
|
|
Analyzing FSM <FSM_1> for best encoding.
|
|
Optimizing FSM <inst_usb_port/s/FSM> on signal <s[1:3]> with gray encoding.
|
|
---------------------
|
|
State | Encoding
|
|
---------------------
|
|
start | 000
|
|
reset | 001
|
|
idle | 011
|
|
leadin | 010
|
|
pulse | 110
|
|
leadout | 111
|
|
release | 101
|
|
---------------------
|
|
Analyzing FSM <FSM_0> for best encoding.
|
|
Optimizing FSM <inst_flash_port/s/FSM> on signal <s[1:3]> with sequential encoding.
|
|
---------------------
|
|
State | Encoding
|
|
---------------------
|
|
start | 000
|
|
reset | 001
|
|
idle | 010
|
|
leadin | 011
|
|
pulse | 100
|
|
leadout | unreached
|
|
release | 101
|
|
---------------------
|
|
Analyzing FSM <FSM_10> for best encoding.
|
|
Optimizing FSM <inst_ps2_phy_0/Inst_debounce_clk/debounce_cs> on signal <debounce_cs[1:2]> with gray encoding.
|
|
Optimizing FSM <inst_ps2_phy_1/Inst_debounce_clk/debounce_cs> on signal <debounce_cs[1:2]> with gray encoding.
|
|
Optimizing FSM <inst_ps2_phy_0/Inst_debounce_data/debounce_cs> on signal <debounce_cs[1:2]> with gray encoding.
|
|
Optimizing FSM <inst_ps2_phy_1/Inst_debounce_data/debounce_cs> on signal <debounce_cs[1:2]> with gray encoding.
|
|
---------------------
|
|
State | Encoding
|
|
---------------------
|
|
init_st | 00
|
|
wait_st | 01
|
|
rel_st | 11
|
|
---------------------
|
|
Loading device for application Rf_Device from file '4vsx35.nph' in environment C:\Programme\Xilinx101\ISE.
|
|
WARNING:Xst:2404 - FFs/Latches <dout<7:4>> (without init value) have a constant value of 0 in block <lcd_port>.
|
|
WARNING:Xst:2404 - FFs/Latches <vlcd.d<3:0>> (without init value) have a constant value of 0 in block <lcd_port>.
|
|
WARNING:Xst:2404 - FFs/Latches <vga_fb_back<31:0>> (without init value) have a constant value of 0 in block <vga_frontend64>.
|
|
WARNING:Xst:2404 - FFs/Latches <blit_nx<31:31>> (without init value) have a constant value of 0 in block <vga_frontend64>.
|
|
|
|
Synthesizing (advanced) Unit <char_gen>.
|
|
INFO:Xst - In order to maximize performance and save block RAM resources, the small ROM <Mrom_cursor_rom_data_rom0000> will be implemented on LUT. If you want to force its implementation on block, use option/constraint rom_style.
|
|
Unit <char_gen> synthesized (advanced).
|
|
|
|
Synthesizing (advanced) Unit <char_rom>.
|
|
INFO:Xst - The ROM <Mrom_DATA_rom0000> will be implemented as a read-only BLOCK RAM, absorbing the register: <DATA>.
|
|
INFO:Xst - The RAM <Mrom_DATA_rom0000> will be implemented as BLOCK RAM
|
|
-----------------------------------------------------------------------
|
|
| ram_type | Block | |
|
|
-----------------------------------------------------------------------
|
|
| Port A |
|
|
| aspect ratio | 4096-word x 8-bit | |
|
|
| mode | write-first | |
|
|
| clkA | connected to signal <CLK> | rise |
|
|
| weA | connected to internal node | high |
|
|
| addrA | connected to signal <ADDR> | |
|
|
| diA | connected to internal node | |
|
|
| doA | connected to signal <DATA> | |
|
|
-----------------------------------------------------------------------
|
|
| optimization | speed | |
|
|
-----------------------------------------------------------------------
|
|
Unit <char_rom> synthesized (advanced).
|
|
|
|
Synthesizing (advanced) Unit <dpram_1w1r_1>.
|
|
INFO:Xst - The RAM <Mram_RAM> will be implemented as a BLOCK RAM, absorbing the following register(s): <dout_b>
|
|
-----------------------------------------------------------------------
|
|
| ram_type | Block | |
|
|
-----------------------------------------------------------------------
|
|
| Port A |
|
|
| aspect ratio | 32-word x 30-bit | |
|
|
| mode | write-first | |
|
|
| clkA | connected to signal <clka> | rise |
|
|
| weA | connected to signal <we_a> | high |
|
|
| addrA | connected to signal <addr_a> | |
|
|
| diA | connected to signal <din_a> | |
|
|
-----------------------------------------------------------------------
|
|
| optimization | speed | |
|
|
-----------------------------------------------------------------------
|
|
| Port B |
|
|
| aspect ratio | 32-word x 30-bit | |
|
|
| mode | read-first | |
|
|
| clkB | connected to signal <clkb> | rise |
|
|
| addrB | connected to signal <addr_b> | |
|
|
| doB | connected to signal <dout_b> | |
|
|
-----------------------------------------------------------------------
|
|
| optimization | speed | |
|
|
-----------------------------------------------------------------------
|
|
Unit <dpram_1w1r_1> synthesized (advanced).
|
|
|
|
Synthesizing (advanced) Unit <dpram_1w1r_2>.
|
|
INFO:Xst - The RAM <Mram_RAM> will be implemented as a BLOCK RAM, absorbing the following register(s): <dout_b>
|
|
-----------------------------------------------------------------------
|
|
| ram_type | Block | |
|
|
-----------------------------------------------------------------------
|
|
| Port A |
|
|
| aspect ratio | 32-word x 72-bit | |
|
|
| mode | write-first | |
|
|
| clkA | connected to signal <clka> | rise |
|
|
| weA | connected to signal <we_a> | high |
|
|
| addrA | connected to signal <addr_a> | |
|
|
| diA | connected to signal <din_a> | |
|
|
-----------------------------------------------------------------------
|
|
| optimization | speed | |
|
|
-----------------------------------------------------------------------
|
|
| Port B |
|
|
| aspect ratio | 32-word x 72-bit | |
|
|
| mode | read-first | |
|
|
| clkB | connected to signal <clkb> | rise |
|
|
| addrB | connected to signal <addr_b> | |
|
|
| doB | connected to signal <dout_b> | |
|
|
-----------------------------------------------------------------------
|
|
| optimization | speed | |
|
|
-----------------------------------------------------------------------
|
|
Unit <dpram_1w1r_2> synthesized (advanced).
|
|
|
|
Synthesizing (advanced) Unit <dpram_1w1r_3>.
|
|
INFO:Xst - The RAM <Mram_RAM> will be implemented as a BLOCK RAM, absorbing the following register(s): <dout_b>
|
|
-----------------------------------------------------------------------
|
|
| ram_type | Block | |
|
|
-----------------------------------------------------------------------
|
|
| Port A |
|
|
| aspect ratio | 32-word x 64-bit | |
|
|
| mode | write-first | |
|
|
| clkA | connected to signal <clka> | rise |
|
|
| weA | connected to signal <we_a> | high |
|
|
| addrA | connected to signal <addr_a> | |
|
|
| diA | connected to signal <din_a> | |
|
|
-----------------------------------------------------------------------
|
|
| optimization | speed | |
|
|
-----------------------------------------------------------------------
|
|
| Port B |
|
|
| aspect ratio | 32-word x 64-bit | |
|
|
| mode | read-first | |
|
|
| clkB | connected to signal <clkb> | rise |
|
|
| addrB | connected to signal <addr_b> | |
|
|
| doB | connected to signal <dout_b> | |
|
|
-----------------------------------------------------------------------
|
|
| optimization | speed | |
|
|
-----------------------------------------------------------------------
|
|
Unit <dpram_1w1r_3> synthesized (advanced).
|
|
|
|
Synthesizing (advanced) Unit <dpram_1w1r_4>.
|
|
INFO:Xst - The RAM <Mram_RAM> will be implemented as a BLOCK RAM, absorbing the following register(s): <dout_b>
|
|
-----------------------------------------------------------------------
|
|
| ram_type | Block | |
|
|
-----------------------------------------------------------------------
|
|
| Port A |
|
|
| aspect ratio | 2048-word x 64-bit | |
|
|
| mode | write-first | |
|
|
| clkA | connected to signal <clka> | rise |
|
|
| weA | connected to signal <we_a> | high |
|
|
| addrA | connected to signal <addr_a> | |
|
|
| diA | connected to signal <din_a> | |
|
|
-----------------------------------------------------------------------
|
|
| optimization | speed | |
|
|
-----------------------------------------------------------------------
|
|
| Port B |
|
|
| aspect ratio | 2048-word x 64-bit | |
|
|
| mode | read-first | |
|
|
| clkB | connected to signal <clkb> | rise |
|
|
| addrB | connected to signal <addr_b> | |
|
|
| doB | connected to signal <dout_b> | |
|
|
-----------------------------------------------------------------------
|
|
| optimization | speed | |
|
|
-----------------------------------------------------------------------
|
|
Unit <dpram_1w1r_4> synthesized (advanced).
|
|
|
|
Synthesizing (advanced) Unit <dpram_1w1r_5>.
|
|
INFO:Xst - The RAM <Mram_RAM> will be implemented as a BLOCK RAM, absorbing the following register(s): <dout_b>
|
|
-----------------------------------------------------------------------
|
|
| ram_type | Block | |
|
|
-----------------------------------------------------------------------
|
|
| Port A |
|
|
| aspect ratio | 512-word x 64-bit | |
|
|
| mode | write-first | |
|
|
| clkA | connected to signal <clka> | rise |
|
|
| weA | connected to signal <we_a> | high |
|
|
| addrA | connected to signal <addr_a> | |
|
|
| diA | connected to signal <din_a> | |
|
|
-----------------------------------------------------------------------
|
|
| optimization | speed | |
|
|
-----------------------------------------------------------------------
|
|
| Port B |
|
|
| aspect ratio | 512-word x 64-bit | |
|
|
| mode | read-first | |
|
|
| clkB | connected to signal <clkb> | rise |
|
|
| addrB | connected to signal <addr_b> | |
|
|
| doB | connected to signal <dout_b> | |
|
|
-----------------------------------------------------------------------
|
|
| optimization | speed | |
|
|
-----------------------------------------------------------------------
|
|
Unit <dpram_1w1r_5> synthesized (advanced).
|
|
|
|
Synthesizing (advanced) Unit <dpram_1w1r_6>.
|
|
INFO:Xst - The small RAM <Mram_RAM> will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style.
|
|
-----------------------------------------------------------------------
|
|
| ram_type | Distributed | |
|
|
-----------------------------------------------------------------------
|
|
| Port A |
|
|
| aspect ratio | 4-word x 105-bit | |
|
|
| clkA | connected to signal <clka> | rise |
|
|
| weA | connected to signal <we_a> | high |
|
|
| addrA | connected to signal <addr_a> | |
|
|
| diA | connected to signal <din_a> | |
|
|
-----------------------------------------------------------------------
|
|
| Port B |
|
|
| aspect ratio | 4-word x 105-bit | |
|
|
| addrB | connected to signal <addr_b> | |
|
|
| doB | connected to internal node | |
|
|
-----------------------------------------------------------------------
|
|
Unit <dpram_1w1r_6> synthesized (advanced).
|
|
|
|
Synthesizing (advanced) Unit <dpram_1w1r_7>.
|
|
INFO:Xst - The RAM <Mram_RAM> will be implemented as a BLOCK RAM, absorbing the following register(s): <dout_b>
|
|
-----------------------------------------------------------------------
|
|
| ram_type | Block | |
|
|
-----------------------------------------------------------------------
|
|
| Port A |
|
|
| aspect ratio | 4096-word x 8-bit | |
|
|
| mode | write-first | |
|
|
| clkA | connected to signal <clka> | rise |
|
|
| weA | connected to signal <we_a> | high |
|
|
| addrA | connected to signal <addr_a> | |
|
|
| diA | connected to signal <din_a> | |
|
|
-----------------------------------------------------------------------
|
|
| optimization | speed | |
|
|
-----------------------------------------------------------------------
|
|
| Port B |
|
|
| aspect ratio | 4096-word x 8-bit | |
|
|
| mode | read-first | |
|
|
| clkB | connected to signal <clkb> | rise |
|
|
| addrB | connected to signal <addr_b> | |
|
|
| doB | connected to signal <dout_b> | |
|
|
-----------------------------------------------------------------------
|
|
| optimization | speed | |
|
|
-----------------------------------------------------------------------
|
|
Unit <dpram_1w1r_7> synthesized (advanced).
|
|
|
|
Synthesizing (advanced) Unit <dpram_1w1r_8>.
|
|
INFO:Xst - The RAM <Mram_RAM> will be implemented as a BLOCK RAM, absorbing the following register(s): <dout_b>
|
|
-----------------------------------------------------------------------
|
|
| ram_type | Block | |
|
|
-----------------------------------------------------------------------
|
|
| Port A |
|
|
| aspect ratio | 256-word x 18-bit | |
|
|
| mode | write-first | |
|
|
| clkA | connected to signal <clka> | rise |
|
|
| weA | connected to signal <we_a> | high |
|
|
| addrA | connected to signal <addr_a> | |
|
|
| diA | connected to signal <din_a> | |
|
|
-----------------------------------------------------------------------
|
|
| optimization | speed | |
|
|
-----------------------------------------------------------------------
|
|
| Port B |
|
|
| aspect ratio | 256-word x 18-bit | |
|
|
| mode | read-first | |
|
|
| clkB | connected to signal <clkb> | rise |
|
|
| addrB | connected to signal <addr_b> | |
|
|
| doB | connected to signal <dout_b> | |
|
|
-----------------------------------------------------------------------
|
|
| optimization | speed | |
|
|
-----------------------------------------------------------------------
|
|
Unit <dpram_1w1r_8> synthesized (advanced).
|
|
|
|
Synthesizing (advanced) Unit <dpram_1w1r_9>.
|
|
INFO:Xst - The RAM <Mram_RAM> will be implemented as a BLOCK RAM, absorbing the following register(s): <dout_b>
|
|
-----------------------------------------------------------------------
|
|
| ram_type | Block | |
|
|
-----------------------------------------------------------------------
|
|
| Port A |
|
|
| aspect ratio | 32-word x 32-bit | |
|
|
| mode | write-first | |
|
|
| clkA | connected to signal <clka> | rise |
|
|
| weA | connected to signal <we_a> | high |
|
|
| addrA | connected to signal <addr_a> | |
|
|
| diA | connected to signal <din_a> | |
|
|
-----------------------------------------------------------------------
|
|
| optimization | speed | |
|
|
-----------------------------------------------------------------------
|
|
| Port B |
|
|
| aspect ratio | 32-word x 32-bit | |
|
|
| mode | read-first | |
|
|
| clkB | connected to signal <clkb> | rise |
|
|
| addrB | connected to signal <addr_b> | |
|
|
| doB | connected to signal <dout_b> | |
|
|
-----------------------------------------------------------------------
|
|
| optimization | speed | |
|
|
-----------------------------------------------------------------------
|
|
Unit <dpram_1w1r_9> synthesized (advanced).
|
|
|
|
Synthesizing (advanced) Unit <rom>.
|
|
INFO:Xst - The RAM <Mram_word_array> will be implemented as a BLOCK RAM, absorbing the following register(s): <jtag_ld_dout> <dout>
|
|
-----------------------------------------------------------------------
|
|
| ram_type | Block | |
|
|
-----------------------------------------------------------------------
|
|
| Port A |
|
|
| aspect ratio | 2048-word x 32-bit | |
|
|
| mode | no-change | |
|
|
| clkA | connected to signal <bs_update1> | rise |
|
|
| weA | connected to signal <bs_sel> | high |
|
|
| addrA | connected to signal <user_regi> | |
|
|
| diA | connected to signal <user_regi> | |
|
|
| doA | connected to signal <jtag_ld_dout> | |
|
|
-----------------------------------------------------------------------
|
|
| optimization | speed | |
|
|
-----------------------------------------------------------------------
|
|
| Port B |
|
|
| aspect ratio | 2048-word x 32-bit | |
|
|
| mode | write-first | |
|
|
| clkB | connected to signal <clk> | rise |
|
|
| enB | connected to signal <ce> | high |
|
|
| addrB | connected to signal <addr> | |
|
|
| doB | connected to signal <dout> | |
|
|
-----------------------------------------------------------------------
|
|
| optimization | speed | |
|
|
-----------------------------------------------------------------------
|
|
Unit <rom> synthesized (advanced).
|
|
WARNING:Xst:1710 - FF/Latch <vlcd.rw> (without init value) has a constant value of 1 in block <lcd_port>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <vlcd.e> (without init value) has a constant value of 0 in block <lcd_port>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <vlcd.rs> (without init value) has a constant value of 0 in block <lcd_port>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:2677 - Node <ADDR_I_r_0> of sequential type is unconnected in block <async_port_wb_1>.
|
|
WARNING:Xst:2677 - Node <ADDR_I_r_1> of sequential type is unconnected in block <async_port_wb_1>.
|
|
WARNING:Xst:2677 - Node <ADDR_I_r_2> of sequential type is unconnected in block <async_port_wb_1>.
|
|
WARNING:Xst:2677 - Node <ADDR_I_r_3> of sequential type is unconnected in block <async_port_wb_1>.
|
|
WARNING:Xst:2677 - Node <row_addr_last_10> of sequential type is unconnected in block <sdram_ctrl>.
|
|
INFO:Xst:2261 - The FF/Latch <input_last> in Unit <debounce> is equivalent to the following FF/Latch, which will be removed : <output>
|
|
INFO:Xst:2261 - The FF/Latch <we_reg> in Unit <ddr_phy> is equivalent to the following FF/Latch, which will be removed : <sdr_data_req_w>
|
|
INFO:Xst:2261 - The FF/Latch <drive270_10> in Unit <ddr_phy> is equivalent to the following 31 FFs/Latches, which will be removed : <drive270_11> <drive270_14> <drive270_12> <drive270_13> <drive270_15> <drive270_20> <drive270_16> <drive270_21> <drive270_0> <drive270_17> <drive270_22> <drive270_23> <drive270_18> <drive270_1> <drive270_2> <drive270_19> <drive270_24> <drive270_30> <drive270_25> <drive270_26> <drive270_3> <drive270_31> <drive270_4> <drive270_27> <drive270_28> <drive270_5> <drive270_29> <drive270_6> <drive270_7> <drive270_8> <drive270_9>
|
|
INFO:Xst:2261 - The FF/Latch <dqs_zen_0> in Unit <ddr_phy> is equivalent to the following 3 FFs/Latches, which will be removed : <dqs_zen_1> <dqs_zen_2> <dqs_zen_3>
|
|
WARNING:Xst:1710 - FF/Latch <DAT_O_10> (without init value) has a constant value of 0 in block <ps2_wb>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <DAT_O_12> (without init value) has a constant value of 0 in block <ps2_wb>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <DAT_O_13> (without init value) has a constant value of 0 in block <ps2_wb>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <DAT_O_14> (without init value) has a constant value of 0 in block <ps2_wb>. This FF/Latch will be trimmed during the optimization process.
|
|
INFO:Xst:2261 - The FF/Latch <csr_posx_cnt_en> in Unit <char_gen> is equivalent to the following FF/Latch, which will be removed : <a_data_we>
|
|
WARNING:Xst:2677 - Node <tag_0> of sequential type is unconnected in block <ac_in>.
|
|
WARNING:Xst:2677 - Node <tag_1> of sequential type is unconnected in block <ac_in>.
|
|
WARNING:Xst:2677 - Node <tag_2> of sequential type is unconnected in block <ac_in>.
|
|
INFO:Xst:2261 - The FF/Latch <slot_valid_1> in Unit <ac_out> is equivalent to the following FF/Latch, which will be removed : <slot_valid_2>
|
|
WARNING:Xst:1710 - FF/Latch <blit_dimx_src_1_2> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <blit_dimx_src_1_1> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <blit_dimx_src_1_0> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <blit_dimx_src_0_2> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <blit_dimx_src_0_1> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <blit_dimx_src_0_0> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <blit_dimx_dst_2> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <blit_dimx_dst_1> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <blit_dimx_dst_0> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <front_2> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <front_1> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <front_0> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <blit_addr_src_1_2> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <blit_addr_dst_0> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <blit_addr_dst_1> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <blit_addr_dst_2> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <host_fb_front_0> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <host_fb_front_1> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <host_fb_front_2> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <host_fb_back_0> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <host_fb_back_1> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <host_fb_back_2> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <blit_addr_src_0_0> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <blit_addr_src_0_1> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <blit_addr_src_0_2> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <blit_addr_src_1_0> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <blit_addr_src_1_1> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <vga_fb_front_0> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <vga_fb_front_1> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <vga_fb_front_2> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
|
|
INFO:Xst:2261 - The FF/Latch <host_blit_nx_25> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_24>
|
|
INFO:Xst:2261 - The FF/Latch <host_blit_nx_30> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_29>
|
|
INFO:Xst:2261 - The FF/Latch <host_blit_nx_31> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_30>
|
|
INFO:Xst:2261 - The FF/Latch <host_blit_nx_26> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_25>
|
|
INFO:Xst:2261 - The FF/Latch <host_blit_nx_27> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_26>
|
|
INFO:Xst:2261 - The FF/Latch <host_blit_nx_28> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_27>
|
|
INFO:Xst:2261 - The FF/Latch <host_blit_nx_29> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_28>
|
|
INFO:Xst:2261 - The FF/Latch <host_blit_nx_1> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_0>
|
|
INFO:Xst:2261 - The FF/Latch <host_blit_nx_2> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_1>
|
|
INFO:Xst:2261 - The FF/Latch <host_blit_nx_3> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_2>
|
|
INFO:Xst:2261 - The FF/Latch <host_blit_nx_4> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_3>
|
|
INFO:Xst:2261 - The FF/Latch <host_blit_nx_5> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_4>
|
|
INFO:Xst:2261 - The FF/Latch <host_blit_nx_6> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_5>
|
|
INFO:Xst:2261 - The FF/Latch <host_blit_nx_7> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_6>
|
|
INFO:Xst:2261 - The FF/Latch <host_blit_nx_8> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_7>
|
|
INFO:Xst:2261 - The FF/Latch <host_blit_nx_9> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_8>
|
|
INFO:Xst:2261 - The FF/Latch <host_blit_nx_10> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_9>
|
|
INFO:Xst:2261 - The FF/Latch <host_blit_nx_11> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_10>
|
|
INFO:Xst:2261 - The FF/Latch <host_blit_nx_12> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_11>
|
|
INFO:Xst:2261 - The FF/Latch <host_blit_nx_13> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_12>
|
|
INFO:Xst:2261 - The FF/Latch <host_blit_nx_14> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_13>
|
|
INFO:Xst:2261 - The FF/Latch <host_blit_nx_15> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_14>
|
|
INFO:Xst:2261 - The FF/Latch <host_blit_nx_20> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_19>
|
|
INFO:Xst:2261 - The FF/Latch <host_blit_nx_16> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_15>
|
|
INFO:Xst:2261 - The FF/Latch <host_blit_nx_21> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_20>
|
|
INFO:Xst:2261 - The FF/Latch <host_blit_nx_17> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_16>
|
|
INFO:Xst:2261 - The FF/Latch <host_blit_nx_22> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_21>
|
|
INFO:Xst:2261 - The FF/Latch <host_blit_nx_18> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_17>
|
|
INFO:Xst:2261 - The FF/Latch <host_blit_nx_23> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_22>
|
|
INFO:Xst:2261 - The FF/Latch <host_blit_nx_19> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_18>
|
|
INFO:Xst:2261 - The FF/Latch <host_blit_nx_24> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_23>
|
|
WARNING:Xst:1710 - FF/Latch <ac_cmd_data_0> (without init value) has a constant value of 0 in block <ac97_wb>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ac_cmd_data_1> (without init value) has a constant value of 0 in block <ac97_wb>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ac_cmd_data_2> (without init value) has a constant value of 0 in block <ac97_wb>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ac_cmd_data_3> (without init value) has a constant value of 0 in block <ac97_wb>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ac_cmd_addr_0> (without init value) has a constant value of 0 in block <ac97_wb>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ac_cmd_addr_1> (without init value) has a constant value of 0 in block <ac97_wb>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ac_cmd_addr_2> (without init value) has a constant value of 0 in block <ac97_wb>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ac_cmd_addr_3> (without init value) has a constant value of 0 in block <ac97_wb>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ac_cmd_addr_4> (without init value) has a constant value of 0 in block <ac97_wb>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ac_cmd_addr_5> (without init value) has a constant value of 0 in block <ac97_wb>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ac_cmd_addr_6> (without init value) has a constant value of 0 in block <ac97_wb>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ac_cmd_addr_7> (without init value) has a constant value of 0 in block <ac97_wb>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ac_cmd_addr_8> (without init value) has a constant value of 0 in block <ac97_wb>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ac_cmd_addr_9> (without init value) has a constant value of 0 in block <ac97_wb>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ac_cmd_addr_10> (without init value) has a constant value of 0 in block <ac97_wb>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ac_cmd_addr_11> (without init value) has a constant value of 0 in block <ac97_wb>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1710 - FF/Latch <data_array_2_3> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <data_array_2_2> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <data_array_2_1> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <data_array_2_0> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <data_array_1_11> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <data_array_1_10> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <data_array_1_9> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <data_array_1_8> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <data_array_1_7> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <data_array_1_6> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <data_array_1_5> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <data_array_1_4> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <data_array_1_3> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <data_array_1_2> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <data_array_1_1> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <data_array_1_0> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1710 - FF/Latch <gpi1_reg_31> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <gpi1_reg_30> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <gpi1_reg_29> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <gpi1_reg_28> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <gpi1_reg_27> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <gpi1_reg_26> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <data_array_12_1> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <data_array_12_0> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <data_array_11_1> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <data_array_11_0> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <data_array_10_1> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <data_array_10_0> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <data_array_9_1> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <data_array_9_0> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <data_array_8_1> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <data_array_8_0> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <data_array_7_1> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <data_array_7_0> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <tx_reg_1> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <tx_reg_0> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <data_array_6_1> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <data_array_6_0> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <data_array_5_1> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <data_array_5_0> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1710 - FF/Latch <data_array_4_1> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1710 - FF/Latch <data_array_4_0> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <data_array_3_1> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <data_array_3_0> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1710 - FF/Latch <gpi0_reg_26> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1710 - FF/Latch <gpi0_reg_25> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1710 - FF/Latch <gpi0_reg_24> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1710 - FF/Latch <gpi0_reg_23> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1710 - FF/Latch <gpi0_reg_22> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1710 - FF/Latch <gpi0_reg_21> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1710 - FF/Latch <gpi0_reg_20> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1710 - FF/Latch <gpi0_reg_19> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1710 - FF/Latch <gpi0_reg_18> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1710 - FF/Latch <gpi0_reg_17> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1710 - FF/Latch <gpi0_reg_16> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1710 - FF/Latch <gpi0_reg_15> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1710 - FF/Latch <gpi0_reg_14> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1710 - FF/Latch <gpi0_reg_13> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1710 - FF/Latch <gpi0_reg_12> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1710 - FF/Latch <gpi0_reg_11> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1710 - FF/Latch <gpi0_reg_10> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1710 - FF/Latch <gpi0_reg_9> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <gpi0_reg_8> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <gpi0_reg_7> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <gpi0_reg_6> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1710 - FF/Latch <gpi0_reg_5> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1710 - FF/Latch <gpi1_reg_25> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <gpi1_reg_24> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1710 - FF/Latch <gpi1_reg_23> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1710 - FF/Latch <gpi1_reg_22> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1710 - FF/Latch <gpi1_reg_21> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1710 - FF/Latch <gpi1_reg_20> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
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WARNING:Xst:1710 - FF/Latch <gpi1_reg_19> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1710 - FF/Latch <gpi1_reg_18> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1710 - FF/Latch <gpi1_reg_17> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1710 - FF/Latch <gpi1_reg_16> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
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|
WARNING:Xst:1710 - FF/Latch <gpi1_reg_15> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <gpi1_reg_14> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <gpi1_reg_13> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <gpi1_reg_12> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <gpi1_reg_11> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <gpi1_reg_10> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <gpi1_reg_9> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <gpi1_reg_8> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <gpi0_reg_31> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <gpi0_reg_30> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <gpi0_reg_29> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <gpi0_reg_28> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <gpi0_reg_27> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:2677 - Node <dout_0> of sequential type is unconnected in block <inst_lcd_port>.
|
|
WARNING:Xst:2677 - Node <dout_1> of sequential type is unconnected in block <inst_lcd_port>.
|
|
WARNING:Xst:2677 - Node <dout_2> of sequential type is unconnected in block <inst_lcd_port>.
|
|
WARNING:Xst:2677 - Node <dout_3> of sequential type is unconnected in block <inst_lcd_port>.
|
|
WARNING:Xst:2677 - Node <gpo1_reg_3> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <gpo1_reg_4> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <gpo1_reg_10> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <gpo1_reg_5> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <gpo1_reg_11> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <gpo1_reg_6> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <gpo0_reg_10> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <gpo1_reg_12> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <gpo1_reg_7> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <gpo0_reg_11> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <gpo1_reg_8> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <gpo1_reg_13> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <gpo0_reg_12> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <gpo1_reg_14> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <gpo1_reg_9> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <gpo0_reg_13> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <gpo1_reg_15> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <gpo1_reg_20> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <gpo0_reg_14> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <gpo1_reg_16> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <gpo1_reg_21> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <gpo0_reg_20> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <gpo0_reg_15> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <gpo1_reg_17> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <gpo1_reg_22> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <gpo0_reg_21> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <gpo0_reg_16> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <gpo1_reg_18> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <gpo1_reg_23> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <gpo0_reg_22> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <gpo0_reg_17> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <gpo1_reg_19> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <gpo1_reg_24> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <gpo0_reg_23> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <gpo0_reg_18> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <gpo1_reg_25> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <gpo1_reg_30> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <gpo0_reg_24> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <gpo0_reg_19> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <gpo1_reg_26> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <gpo1_reg_31> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <gpo0_reg_30> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <gpo0_reg_25> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <gpo0_reg_9> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <gpo1_reg_27> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <gpo0_reg_31> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <gpo1_reg_28> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <gpo0_reg_26> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <gpo0_reg_27> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <gpo1_reg_29> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <gpo0_reg_28> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <gpo0_reg_29> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <sys_gpo0_9> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <sys_gpo0_10> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <sys_gpo0_11> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <sys_gpo0_12> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <sys_gpo0_13> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <sys_gpo0_14> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <sys_gpo0_15> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <sys_gpo0_16> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <sys_gpo0_17> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <sys_gpo0_18> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <sys_gpo0_19> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <sys_gpo0_20> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <sys_gpo0_21> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <sys_gpo0_22> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <sys_gpo0_23> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <sys_gpo0_24> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <sys_gpo0_25> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <sys_gpo0_26> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <sys_gpo0_27> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <sys_gpo0_28> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <sys_gpo0_29> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <sys_gpo0_30> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <sys_gpo0_31> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <sys_gpo1_3> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <sys_gpo1_4> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <sys_gpo1_5> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <sys_gpo1_6> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <sys_gpo1_7> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <sys_gpo1_8> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <sys_gpo1_9> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <sys_gpo1_10> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <sys_gpo1_11> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <sys_gpo1_12> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <sys_gpo1_13> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <sys_gpo1_14> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <sys_gpo1_15> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <sys_gpo1_16> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <sys_gpo1_17> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <sys_gpo1_18> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <sys_gpo1_19> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <sys_gpo1_20> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <sys_gpo1_21> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <sys_gpo1_22> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <sys_gpo1_23> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <sys_gpo1_24> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <sys_gpo1_25> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <sys_gpo1_26> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <sys_gpo1_27> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <sys_gpo1_28> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <sys_gpo1_29> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <sys_gpo1_30> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <sys_gpo1_31> of sequential type is unconnected in block <inst_gpio_wb>.
|
|
WARNING:Xst:2677 - Node <async_be_0> of sequential type is unconnected in block <inst_flash_port>.
|
|
WARNING:Xst:2677 - Node <async_a_0> of sequential type is unconnected in block <inst_flash_port>.
|
|
WARNING:Xst:2677 - Node <async_a_1> of sequential type is unconnected in block <inst_flash_port>.
|
|
WARNING:Xst:2677 - Node <async_be_0> of sequential type is unconnected in block <inst_usb_port>.
|
|
WARNING:Xst:2677 - Node <async_rst> of sequential type is unconnected in block <inst_usb_port>.
|
|
WARNING:Xst:2677 - Node <async_a_0> of sequential type is unconnected in block <inst_usb_port>.
|
|
WARNING:Xst:2677 - Node <async_a_1> of sequential type is unconnected in block <inst_usb_port>.
|
|
WARNING:Xst:2677 - Node <fifo_aempty> of sequential type is unconnected in block <inst_fifo_sync_ctrl>.
|
|
WARNING:Xst:2677 - Node <fifo_afull> of sequential type is unconnected in block <inst_fifo_sync_ctrl>.
|
|
WARNING:Xst:2677 - Node <fifo_aempty> of sequential type is unconnected in block <inst_fifo_async_ctrl>.
|
|
WARNING:Xst:2677 - Node <fifo_afull> of sequential type is unconnected in block <inst_fifo_async_ctrl>.
|
|
WARNING:Xst:2677 - Node <fifo_aempty> of sequential type is unconnected in block <inst_fifo_async_ctrl>.
|
|
WARNING:Xst:2677 - Node <fifo_afull> of sequential type is unconnected in block <inst_fifo_async_ctrl>.
|
|
WARNING:Xst:2677 - Node <fifo_aempty> of sequential type is unconnected in block <inst_fifo_async_ctrl>.
|
|
WARNING:Xst:2677 - Node <fifo_afull> of sequential type is unconnected in block <inst_fifo_async_ctrl>.
|
|
WARNING:Xst:2677 - Node <u_tag_pipe_0_1> of sequential type is unconnected in block <inst_ddr_phy>.
|
|
WARNING:Xst:2677 - Node <u_tag_pipe_0_2> of sequential type is unconnected in block <inst_ddr_phy>.
|
|
WARNING:Xst:2677 - Node <u_tag_pipe_0_3> of sequential type is unconnected in block <inst_ddr_phy>.
|
|
WARNING:Xst:2677 - Node <u_tag_pipe_1_1> of sequential type is unconnected in block <inst_ddr_phy>.
|
|
WARNING:Xst:2677 - Node <u_tag_pipe_1_2> of sequential type is unconnected in block <inst_ddr_phy>.
|
|
WARNING:Xst:2677 - Node <u_tag_pipe_1_3> of sequential type is unconnected in block <inst_ddr_phy>.
|
|
WARNING:Xst:2677 - Node <u_tag_wr_1> of sequential type is unconnected in block <inst_ddr_phy>.
|
|
WARNING:Xst:2677 - Node <u_tag_wr_2> of sequential type is unconnected in block <inst_ddr_phy>.
|
|
WARNING:Xst:2677 - Node <u_tag_wr_3> of sequential type is unconnected in block <inst_ddr_phy>.
|
|
WARNING:Xst:2677 - Node <u_tag_pipe_2_1> of sequential type is unconnected in block <inst_ddr_phy>.
|
|
WARNING:Xst:2677 - Node <u_tag_pipe_2_2> of sequential type is unconnected in block <inst_ddr_phy>.
|
|
WARNING:Xst:2677 - Node <u_tag_pipe_2_3> of sequential type is unconnected in block <inst_ddr_phy>.
|
|
WARNING:Xst:2677 - Node <u_tag_pipe_3_1> of sequential type is unconnected in block <inst_ddr_phy>.
|
|
WARNING:Xst:2677 - Node <u_tag_pipe_3_2> of sequential type is unconnected in block <inst_ddr_phy>.
|
|
WARNING:Xst:2677 - Node <u_tag_pipe_3_3> of sequential type is unconnected in block <inst_ddr_phy>.
|
|
WARNING:Xst:2677 - Node <u_tag_pipe_4_1> of sequential type is unconnected in block <inst_ddr_phy>.
|
|
WARNING:Xst:2677 - Node <u_tag_pipe_4_2> of sequential type is unconnected in block <inst_ddr_phy>.
|
|
WARNING:Xst:2677 - Node <u_tag_pipe_4_3> of sequential type is unconnected in block <inst_ddr_phy>.
|
|
WARNING:Xst:2677 - Node <u_tag_rd_1> of sequential type is unconnected in block <inst_ddr_phy>.
|
|
WARNING:Xst:2677 - Node <u_tag_rd_2> of sequential type is unconnected in block <inst_ddr_phy>.
|
|
WARNING:Xst:2677 - Node <u_tag_rd_3> of sequential type is unconnected in block <inst_ddr_phy>.
|
|
WARNING:Xst:2677 - Node <fifo_aempty> of sequential type is unconnected in block <inst_fifo_sync_ctrl>.
|
|
WARNING:Xst:2677 - Node <fifo_afull> of sequential type is unconnected in block <inst_fifo_sync_ctrl>.
|
|
WARNING:Xst:2677 - Node <fifo_aempty> of sequential type is unconnected in block <inst_fifo_sync_ctrl>.
|
|
WARNING:Xst:2677 - Node <fifo_aempty> of sequential type is unconnected in block <inst_fifo_sync_ctrl>.
|
|
WARNING:Xst:2677 - Node <tag_3> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <tag_4> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <tag_5> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <tag_6> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <tag_7> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <tag_8> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <tag_9> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <tag_10> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <data_array_1_0> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <data_array_1_1> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <data_array_4_0> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <data_array_4_1> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <data_array_2_0> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <data_array_2_1> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <data_array_3_0> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <data_array_3_1> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <data_array_7_0> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <data_array_7_1> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <data_array_5_0> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <data_array_5_1> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <data_array_6_0> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <data_array_6_1> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <data_array_10_0> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <data_array_10_1> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <data_array_8_0> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <data_array_8_1> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <data_array_9_0> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <data_array_9_1> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <data_array_11_0> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <data_array_11_1> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <data_array_12_0> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <data_array_12_1> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <stat_data_0> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <stat_data_1> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <stat_data_2> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <stat_data_3> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <stat_addr_0> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <stat_addr_1> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <stat_addr_2> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <stat_addr_3> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <stat_addr_4> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <stat_addr_5> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <stat_addr_6> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <stat_addr_7> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <stat_addr_8> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <stat_addr_9> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <stat_addr_12> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <stat_addr_13> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <stat_addr_14> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <stat_addr_15> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <stat_addr_16> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <stat_addr_17> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <stat_addr_18> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <stat_addr_19> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <slot_valid_12> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <slot_valid_11> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <slot_valid_10> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <slot_valid_9> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <slot_valid_8> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <slot_valid_7> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <slot_valid_6> of sequential type is unconnected in block <inst_ac_in>.
|
|
WARNING:Xst:2677 - Node <slot_valid_5> of sequential type is unconnected in block <inst_ac_in>.
|
|
|
|
=========================================================================
|
|
Advanced HDL Synthesis Report
|
|
|
|
Macro Statistics
|
|
# RAMs : 11
|
|
2048x32-bit dual-port block RAM : 1
|
|
2048x64-bit dual-port block RAM : 1
|
|
256x18-bit dual-port block RAM : 1
|
|
32x30-bit dual-port block RAM : 1
|
|
32x32-bit dual-port block RAM : 1
|
|
32x64-bit dual-port block RAM : 1
|
|
32x72-bit dual-port block RAM : 1
|
|
4096x8-bit dual-port block RAM : 1
|
|
4096x8-bit single-port block RAM : 1
|
|
4x105-bit dual-port distributed RAM : 1
|
|
512x64-bit dual-port block RAM : 1
|
|
# ROMs : 5
|
|
10x4-bit ROM : 1
|
|
15x27-bit ROM : 1
|
|
32x12-bit ROM : 2
|
|
32x8-bit ROM : 1
|
|
# Adders/Subtractors : 53
|
|
10-bit subtractor : 1
|
|
12-bit adder : 7
|
|
12-bit subtractor : 2
|
|
2-bit adder : 2
|
|
2-bit subtractor : 1
|
|
3-bit adder : 1
|
|
3-bit subtractor : 4
|
|
32-bit adder : 7
|
|
5-bit adder : 5
|
|
6-bit adder : 12
|
|
6-bit subtractor : 6
|
|
8-bit adder : 2
|
|
8-bit subtractor : 1
|
|
9-bit adder : 2
|
|
# Counters : 49
|
|
10-bit down counter : 2
|
|
10-bit up counter : 2
|
|
10-bit updown counter : 1
|
|
12-bit up counter : 1
|
|
14-bit down counter : 4
|
|
15-bit down counter : 1
|
|
16-bit up counter : 2
|
|
18-bit up counter : 1
|
|
29-bit up counter : 2
|
|
3-bit down counter : 4
|
|
3-bit updown counter : 1
|
|
32-bit up counter : 6
|
|
4-bit down counter : 1
|
|
4-bit up counter : 4
|
|
5-bit down counter : 3
|
|
5-bit up counter : 5
|
|
6-bit updown counter : 1
|
|
7-bit down counter : 2
|
|
7-bit up counter : 3
|
|
8-bit down counter : 1
|
|
9-bit down counter : 1
|
|
9-bit updown counter : 1
|
|
# Accumulators : 2
|
|
32-bit up loadable accumulator : 2
|
|
# Registers : 3649
|
|
Flip-Flops : 3649
|
|
# Comparators : 71
|
|
10-bit comparator greatequal : 1
|
|
10-bit comparator lessequal : 1
|
|
12-bit comparator equal : 2
|
|
12-bit comparator greatequal : 2
|
|
12-bit comparator lessequal : 1
|
|
13-bit comparator not equal : 1
|
|
16-bit comparator equal : 2
|
|
2-bit comparator equal : 2
|
|
21-bit comparator equal : 1
|
|
29-bit comparator equal : 1
|
|
3-bit comparator greatequal : 1
|
|
3-bit comparator less : 1
|
|
3-bit comparator lessequal : 1
|
|
32-bit comparator equal : 4
|
|
32-bit comparator greatequal : 3
|
|
32-bit comparator less : 3
|
|
32-bit comparator not equal : 4
|
|
4-bit comparator greatequal : 1
|
|
4-bit comparator greater : 1
|
|
4-bit comparator less : 1
|
|
5-bit comparator equal : 3
|
|
5-bit comparator greatequal : 2
|
|
5-bit comparator less : 4
|
|
6-bit comparator equal : 6
|
|
6-bit comparator greatequal : 4
|
|
6-bit comparator lessequal : 4
|
|
7-bit comparator equal : 1
|
|
7-bit comparator greatequal : 3
|
|
7-bit comparator less : 2
|
|
8-bit comparator equal : 2
|
|
8-bit comparator greatequal : 1
|
|
8-bit comparator less : 1
|
|
9-bit comparator equal : 2
|
|
9-bit comparator greatequal : 1
|
|
9-bit comparator lessequal : 1
|
|
# Multiplexers : 6
|
|
1-bit 4-to-1 multiplexer : 1
|
|
32-bit 4-to-1 multiplexer : 4
|
|
64-bit 4-to-1 multiplexer : 1
|
|
# Xors : 60
|
|
1-bit xor2 : 60
|
|
|
|
=========================================================================
|
|
|
|
=========================================================================
|
|
* Low Level Synthesis *
|
|
=========================================================================
|
|
INFO:Xst:2261 - The FF/Latch <gpi0_reg_5> in Unit <gpio_wb> is equivalent to the following 50 FFs/Latches, which will be removed : <gpi0_reg_6> <gpi0_reg_7> <gpi0_reg_8> <gpi0_reg_9> <gpi0_reg_10> <gpi0_reg_11> <gpi0_reg_12> <gpi0_reg_13> <gpi0_reg_14> <gpi0_reg_15> <gpi0_reg_16> <gpi0_reg_17> <gpi0_reg_18> <gpi0_reg_19> <gpi0_reg_20> <gpi0_reg_21> <gpi0_reg_22> <gpi0_reg_23> <gpi0_reg_24> <gpi0_reg_25> <gpi0_reg_26> <gpi0_reg_27> <gpi0_reg_28> <gpi0_reg_29> <gpi0_reg_30> <gpi0_reg_31> <gpi1_reg_8> <gpi1_reg_9> <gpi1_reg_10> <gpi1_reg_11> <gpi1_reg_12> <gpi1_reg_13> <gpi1_reg_14> <gpi1_reg_15> <gpi1_reg_16> <gpi1_reg_17> <gpi1_reg_18> <gpi1_reg_19> <gpi1_reg_20> <gpi1_reg_21> <gpi1_reg_22> <gpi1_reg_23> <gpi1_reg_24> <gpi1_reg_25> <gpi1_reg_26> <gpi1_reg_27> <gpi1_reg_28> <gpi1_reg_29> <gpi1_reg_30> <gpi1_reg_31>
|
|
WARNING:Xst:1710 - FF/Latch <gpi0_reg_5> (without init value) has a constant value of 0 in block <gpio_wb>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/diff_0> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/diff_1> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/diff_2> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/diff_3> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/diff_4> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/diff_5> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/diff0_0> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/diff0_1> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/diff0_2> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/diff0_3> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/diff0_4> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/diff0_5> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/p11_0> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/p11_1> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/p11_2> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/p11_3> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/p11_4> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/p11_5> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/p12_0> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/p12_1> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/p12_2> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/p12_3> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/p12_4> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/p12_5> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/p21_0> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/p21_1> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/p21_2> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/p21_3> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/p21_4> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/p21_5> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/p22_0> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/p22_1> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/p22_2> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/p22_3> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/p22_4> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/p22_5> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/fifo_aempty> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/fifo_afull> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/bcnt2_ar_0> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/bcnt2_ar_1> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/bcnt2_ar_2> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/bcnt2_ar_3> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/bcnt2_ar_4> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/bcnt2_ar_5> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/bcnt2_aw_0> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/bcnt2_aw_1> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/bcnt2_aw_2> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/bcnt2_aw_3> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/bcnt2_aw_4> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/bcnt2_aw_5> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/diff_0> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/diff_1> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/diff_2> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/diff_3> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/diff_4> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/diff_5> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/diff0_0> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/diff0_1> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/diff0_2> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/diff0_3> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/diff0_4> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/diff0_5> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/p11_0> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/p11_1> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/p11_2> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/p11_3> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/p11_4> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/p11_5> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/p12_0> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/p12_1> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/p12_2> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/p12_3> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/p12_4> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/p12_5> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/p21_0> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/p21_1> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/p21_2> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/p21_3> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/p21_4> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/p21_5> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/p22_0> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/p22_1> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/p22_2> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/p22_3> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/p22_4> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/p22_5> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/fifo_aempty> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/fifo_afull> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/bcnt2_ar_0> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/bcnt2_ar_1> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/bcnt2_ar_2> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/bcnt2_ar_3> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/bcnt2_ar_4> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/bcnt2_ar_5> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/bcnt2_aw_0> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/bcnt2_aw_1> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/bcnt2_aw_2> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/bcnt2_aw_3> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/bcnt2_aw_4> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/bcnt2_aw_5> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/bcnt2_aw_5> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/bcnt2_aw_4> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/bcnt2_aw_3> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/bcnt2_aw_2> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/bcnt2_aw_1> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/bcnt2_aw_0> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/bcnt2_ar_5> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/bcnt2_ar_4> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/bcnt2_ar_3> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/bcnt2_ar_2> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/bcnt2_ar_1> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/bcnt2_ar_0> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/fifo_afull> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/fifo_aempty> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p22_5> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p22_4> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p22_3> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p22_2> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p22_1> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p22_0> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p21_5> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p21_4> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p21_3> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p21_2> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p21_1> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p21_0> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p12_5> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p12_4> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p12_3> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p12_2> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p12_1> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p12_0> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p11_5> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p11_4> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p11_3> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p11_2> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p11_1> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p11_0> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/diff0_5> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/diff0_4> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/diff0_3> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/diff0_2> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/diff0_1> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/diff0_0> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/diff_5> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/diff_4> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/diff_3> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/diff_2> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/diff_1> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/diff_0> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
|
|
WARNING:Xst:2677 - Node <inst_lcd_port/dout_3> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_lcd_port/dout_2> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_lcd_port/dout_1> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_lcd_port/dout_0> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <diff0_0> of sequential type is unconnected in block <fifo_async_ctrl_2>.
|
|
WARNING:Xst:1710 - FF/Latch <blit_src_offset_0> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <blit_src_offset_1> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <blit_src_offset_2> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <blit_dst_offset_0> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <blit_dst_offset_1> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <blit_dst_offset_2> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <blit_src_off_y_0> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <blit_src_off_y_1> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <blit_src_off_y_2> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <blit_dst_off_y_0> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <blit_dst_off_y_1> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <blit_dst_off_y_2> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:2677 - Node <data_reg_18> of sequential type is unconnected in block <ac97_wb>.
|
|
WARNING:Xst:2677 - Node <data_reg_19> of sequential type is unconnected in block <ac97_wb>.
|
|
WARNING:Xst:2677 - Node <data_reg_20> of sequential type is unconnected in block <ac97_wb>.
|
|
WARNING:Xst:2677 - Node <data_reg_21> of sequential type is unconnected in block <ac97_wb>.
|
|
WARNING:Xst:2677 - Node <data_reg_22> of sequential type is unconnected in block <ac97_wb>.
|
|
WARNING:Xst:2677 - Node <data_reg_23> of sequential type is unconnected in block <ac97_wb>.
|
|
WARNING:Xst:2677 - Node <data_reg_24> of sequential type is unconnected in block <ac97_wb>.
|
|
WARNING:Xst:2677 - Node <data_reg_25> of sequential type is unconnected in block <ac97_wb>.
|
|
WARNING:Xst:2677 - Node <data_reg_26> of sequential type is unconnected in block <ac97_wb>.
|
|
WARNING:Xst:2677 - Node <data_reg_27> of sequential type is unconnected in block <ac97_wb>.
|
|
WARNING:Xst:2677 - Node <data_reg_28> of sequential type is unconnected in block <ac97_wb>.
|
|
WARNING:Xst:2677 - Node <data_reg_29> of sequential type is unconnected in block <ac97_wb>.
|
|
WARNING:Xst:2677 - Node <data_reg_30> of sequential type is unconnected in block <ac97_wb>.
|
|
WARNING:Xst:2677 - Node <data_reg_31> of sequential type is unconnected in block <ac97_wb>.
|
|
WARNING:Xst:2677 - Node <addr_reg_0> of sequential type is unconnected in block <ac97_wb>.
|
|
WARNING:Xst:2677 - Node <addr_reg_1> of sequential type is unconnected in block <ac97_wb>.
|
|
WARNING:Xst:2677 - Node <addr_reg_10> of sequential type is unconnected in block <ac97_wb>.
|
|
WARNING:Xst:2677 - Node <addr_reg_11> of sequential type is unconnected in block <ac97_wb>.
|
|
WARNING:Xst:2677 - Node <addr_reg_12> of sequential type is unconnected in block <ac97_wb>.
|
|
WARNING:Xst:2677 - Node <addr_reg_13> of sequential type is unconnected in block <ac97_wb>.
|
|
WARNING:Xst:2677 - Node <addr_reg_14> of sequential type is unconnected in block <ac97_wb>.
|
|
WARNING:Xst:2677 - Node <addr_reg_15> of sequential type is unconnected in block <ac97_wb>.
|
|
WARNING:Xst:2677 - Node <addr_reg_16> of sequential type is unconnected in block <ac97_wb>.
|
|
WARNING:Xst:2677 - Node <addr_reg_17> of sequential type is unconnected in block <ac97_wb>.
|
|
WARNING:Xst:2677 - Node <addr_reg_18> of sequential type is unconnected in block <ac97_wb>.
|
|
WARNING:Xst:2677 - Node <addr_reg_19> of sequential type is unconnected in block <ac97_wb>.
|
|
WARNING:Xst:2677 - Node <addr_reg_20> of sequential type is unconnected in block <ac97_wb>.
|
|
WARNING:Xst:2677 - Node <addr_reg_21> of sequential type is unconnected in block <ac97_wb>.
|
|
WARNING:Xst:2677 - Node <addr_reg_22> of sequential type is unconnected in block <ac97_wb>.
|
|
WARNING:Xst:2677 - Node <addr_reg_23> of sequential type is unconnected in block <ac97_wb>.
|
|
WARNING:Xst:2677 - Node <addr_reg_24> of sequential type is unconnected in block <ac97_wb>.
|
|
WARNING:Xst:2677 - Node <addr_reg_25> of sequential type is unconnected in block <ac97_wb>.
|
|
WARNING:Xst:2677 - Node <addr_reg_26> of sequential type is unconnected in block <ac97_wb>.
|
|
WARNING:Xst:2677 - Node <addr_reg_27> of sequential type is unconnected in block <ac97_wb>.
|
|
WARNING:Xst:2677 - Node <addr_reg_28> of sequential type is unconnected in block <ac97_wb>.
|
|
WARNING:Xst:2677 - Node <addr_reg_29> of sequential type is unconnected in block <ac97_wb>.
|
|
WARNING:Xst:2677 - Node <addr_reg_30> of sequential type is unconnected in block <ac97_wb>.
|
|
WARNING:Xst:2677 - Node <addr_reg_31> of sequential type is unconnected in block <ac97_wb>.
|
|
INFO:Xst:1901 - Instance inst_DCM_VGA_FX in unit clockgen of type DCM_BASE has been replaced by DCM_ADV
|
|
INFO:Xst:1901 - Instance inst_DCM_SYS_FX in unit clockgen of type DCM_BASE has been replaced by DCM_ADV
|
|
INFO:Xst:1901 - Instance inst_DCM_SDRCLK_0 in unit clockgen of type DCM_BASE has been replaced by DCM_ADV
|
|
INFO:Xst:1901 - Instance inst_DCM_SDRCLK_1 in unit clockgen of type DCM_BASE has been replaced by DCM_ADV
|
|
WARNING:Xst:2677 - Node <inst_flash_port/async_a_1> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_flash_port/async_a_0> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_flash_port/async_be_0> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_usb_port/async_a_1> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_usb_port/async_a_0> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_usb_port/async_rst> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_usb_port/async_be_0> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/u_tag_pipe_0_1> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/u_tag_pipe_0_2> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/u_tag_pipe_0_3> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/u_tag_pipe_1_1> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/u_tag_pipe_1_2> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/u_tag_pipe_1_3> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/u_tag_wr_1> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/u_tag_wr_2> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/u_tag_wr_3> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/u_tag_pipe_2_1> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/u_tag_pipe_2_2> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/u_tag_pipe_2_3> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/u_tag_pipe_3_1> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/u_tag_pipe_3_2> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/u_tag_pipe_3_3> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/u_tag_pipe_4_1> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/u_tag_pipe_4_2> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/u_tag_pipe_4_3> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/u_tag_rd_1> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/u_tag_rd_2> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/u_tag_rd_3> of sequential type is unconnected in block <mips_sys>.
|
|
INFO:Xst:2261 - The FF/Latch <cursor_rom_data_0> in Unit <char_gen> is equivalent to the following 7 FFs/Latches, which will be removed : <cursor_rom_data_1> <cursor_rom_data_2> <cursor_rom_data_3> <cursor_rom_data_4> <cursor_rom_data_5> <cursor_rom_data_6> <cursor_rom_data_7>
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|
|
|
Optimizing unit <mips_sys> ...
|
|
INFO:Xst:2261 - The FF/Latch <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/p0_2> in Unit <mips_sys> is equivalent to the following FF/Latch, which will be removed : <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/read_en>
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|
|
|
Optimizing unit <gpio_wb> ...
|
|
|
|
Optimizing unit <fifo_sync_ctrl_1> ...
|
|
|
|
Optimizing unit <gray_counter_1> ...
|
|
INFO:Xst:2261 - The FF/Latch <cntb_5> in Unit <gray_counter_1> is equivalent to the following FF/Latch, which will be removed : <cntg_5>
|
|
INFO:Xst:2261 - The FF/Latch <cntb_5> in Unit <gray_counter_1> is equivalent to the following FF/Latch, which will be removed : <cntg_5>
|
|
|
|
Optimizing unit <sdram_ctrl> ...
|
|
|
|
Optimizing unit <sdram_cmd> ...
|
|
WARNING:Xst:1710 - FF/Latch <burst_finished> (without init value) has a constant value of 1 in block <sdram_cmd>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <burst_cnt_1> has a constant value of 0 in block <sdram_cmd>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:2677 - Node <burst_cnt_0> of sequential type is unconnected in block <sdram_cmd>.
|
|
|
|
Optimizing unit <gray_counter_2> ...
|
|
INFO:Xst:2261 - The FF/Latch <cntb_11> in Unit <gray_counter_2> is equivalent to the following FF/Latch, which will be removed : <cntg_11>
|
|
INFO:Xst:2261 - The FF/Latch <cntb_11> in Unit <gray_counter_2> is equivalent to the following FF/Latch, which will be removed : <cntg_11>
|
|
|
|
Optimizing unit <fifo_sync_ctrl_2> ...
|
|
|
|
Optimizing unit <fifo_sync_ctrl_3> ...
|
|
|
|
Optimizing unit <dpram_1w1r_6> ...
|
|
|
|
Optimizing unit <fifo_sync_ctrl_4> ...
|
|
|
|
Optimizing unit <ps2_core> ...
|
|
|
|
Optimizing unit <debounce> ...
|
|
|
|
Optimizing unit <clockgen> ...
|
|
|
|
Optimizing unit <rom> ...
|
|
|
|
Optimizing unit <kcuart_tx> ...
|
|
|
|
Optimizing unit <bbfifo_16x8> ...
|
|
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|
Optimizing unit <kcuart_rx> ...
|
|
|
|
Optimizing unit <char_gen> ...
|
|
|
|
Optimizing unit <fifo_async_ctrl_2> ...
|
|
|
|
Optimizing unit <ac_in> ...
|
|
|
|
Optimizing unit <ac_out> ...
|
|
|
|
Optimizing unit <vga_backend> ...
|
|
|
|
Optimizing unit <ac_io> ...
|
|
|
|
Optimizing unit <vga_frontend64> ...
|
|
|
|
Optimizing unit <ac97_wb> ...
|
|
WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_4_0> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_3_1> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_3_0> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_2_3> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_2_2> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_2_1> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_2_0> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_1_11> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_1_10> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_1_9> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_1_8> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_1_7> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_1_6> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_1_5> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_1_4> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_1_3> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_1_2> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_1_1> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_1_0> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_12_1> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_12_0> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_11_1> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_11_0> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_10_1> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_10_0> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_9_1> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_9_0> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_8_1> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_8_0> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_7_1> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_7_0> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_6_1> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_6_0> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_5_1> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_5_0> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_4_1> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_1> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_0> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo1_31> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo1_30> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo1_29> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo1_28> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo1_27> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo1_26> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo1_25> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo1_24> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo1_23> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo1_22> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo1_21> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo1_20> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo1_19> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo1_18> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo1_17> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo1_16> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo1_15> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo1_14> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo1_13> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo1_12> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo1_11> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo1_10> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo1_9> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo1_8> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo1_7> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo1_6> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo1_5> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo1_4> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo1_3> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo0_31> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo0_30> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo0_29> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo0_28> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo0_27> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo0_26> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo0_25> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo0_24> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo0_23> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo0_22> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo0_21> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo0_20> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo0_19> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo0_18> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo0_17> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo0_16> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo0_15> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo0_14> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo0_13> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo0_12> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo0_11> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo0_10> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo0_9> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/gpo0_reg_29> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/gpo0_reg_28> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/gpo1_reg_29> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/gpo0_reg_27> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/gpo0_reg_26> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/gpo1_reg_28> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/gpo0_reg_31> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/gpo1_reg_27> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/gpo0_reg_9> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/gpo0_reg_25> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/gpo0_reg_30> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/gpo1_reg_31> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/gpo1_reg_26> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/gpo0_reg_19> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/gpo0_reg_24> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/gpo1_reg_30> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/gpo1_reg_25> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/gpo0_reg_18> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/gpo0_reg_23> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/gpo1_reg_24> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/gpo1_reg_19> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/gpo0_reg_17> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/gpo0_reg_22> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/gpo1_reg_23> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/gpo1_reg_18> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/gpo0_reg_16> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/gpo0_reg_21> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/gpo1_reg_22> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/gpo1_reg_17> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/gpo0_reg_15> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/gpo0_reg_20> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/gpo1_reg_21> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/gpo1_reg_16> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/gpo0_reg_14> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/gpo1_reg_20> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/gpo1_reg_15> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/gpo0_reg_13> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/gpo1_reg_9> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/gpo1_reg_14> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/gpo0_reg_12> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/gpo1_reg_13> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/gpo1_reg_8> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/gpo0_reg_11> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/gpo1_reg_7> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/gpo1_reg_12> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/gpo0_reg_10> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/gpo1_reg_6> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/gpo1_reg_11> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/gpo1_reg_5> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/gpo1_reg_10> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/gpo1_reg_4> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_gpio_wb/gpo1_reg_3> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl_frontend_wb/inst_cat_fifo/inst_fifo_sync_ctrl/diff_5> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl_frontend_wb/inst_cat_fifo/inst_fifo_sync_ctrl/diff_4> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl_frontend_wb/inst_cat_fifo/inst_fifo_sync_ctrl/diff_3> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl_frontend_wb/inst_cat_fifo/inst_fifo_sync_ctrl/diff_2> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl_frontend_wb/inst_cat_fifo/inst_fifo_sync_ctrl/diff_1> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl_frontend_wb/inst_cat_fifo/inst_fifo_sync_ctrl/diff_0> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl_frontend_wb/inst_cat_fifo/inst_fifo_sync_ctrl/fifo_afull> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_sdram_ctrl_frontend_wb/inst_cat_fifo/inst_fifo_sync_ctrl/fifo_aempty> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_vga_frontend/inst_bus_fifo/inst_dpram_1w1r/dout_b_0> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_vga_frontend/inst_bus_fifo/inst_dpram_1w1r/dout_b_1> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_vga_frontend/inst_bus_fifo/inst_dpram_1w1r/Mram_RAM1> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_vga_frontend/inst_bus_fifo/inst_dpram_1w1r/Mram_RAM2> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_vga_frontend/inst_bus_fifo/inst_fifo_sync_ctrl/fifo_aempty> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_vga_frontend/inst_bus_fifo/inst_fifo_sync_ctrl/diff_0> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_vga_frontend/inst_bus_fifo/inst_fifo_sync_ctrl/diff_1> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_vga_frontend/inst_bus_fifo/inst_fifo_sync_ctrl/diff_2> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl/fifo_aempty> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl/fifo_afull> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl/diff_0> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl/diff_1> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl/diff_2> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl/diff_3> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl/diff_4> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl/diff_5> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl/diff_6> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl/diff_7> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl/diff_8> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl/diff_9> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM8> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/slot_valid_5> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/slot_valid_6> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/slot_valid_7> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/slot_valid_8> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/slot_valid_9> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/slot_valid_10> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/slot_valid_11> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/slot_valid_12> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/stat_addr_19> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/stat_addr_18> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/stat_addr_17> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/stat_addr_16> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/stat_addr_15> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/stat_addr_14> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/stat_addr_13> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/stat_addr_12> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/stat_addr_9> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/stat_addr_8> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/stat_addr_7> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/stat_addr_6> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/stat_addr_5> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/stat_addr_4> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/stat_addr_3> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/stat_addr_2> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/stat_addr_1> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/stat_addr_0> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/stat_data_3> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/stat_data_2> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/stat_data_1> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/stat_data_0> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_12_1> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_12_0> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_11_1> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_11_0> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_9_1> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_9_0> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_8_1> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_8_0> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_10_1> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_10_0> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_6_1> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_6_0> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_5_1> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_5_0> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_7_1> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_7_0> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_3_1> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_3_0> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_2_3> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_2_2> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_2_1> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_2_0> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_4_1> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_4_0> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_19> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_18> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_17> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_16> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_15> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_14> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_13> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_12> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_9> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_8> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_7> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_6> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_5> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_4> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_3> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_2> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_1> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_0> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/tag_10> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/tag_9> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/tag_8> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/tag_7> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/tag_6> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/tag_5> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/tag_4> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/tag_3> of sequential type is unconnected in block <mips_sys>.
|
|
WARNING:Xst:2677 - Node <inst_ac97_wb/inst_tx_fifo/inst_fifo_sync_ctrl/fifo_aempty> of sequential type is unconnected in block <mips_sys>.
|
|
|
|
Mapping all equations...
|
|
WARNING:Xst:2036 - Inserting OBUF on port <sys_error<1>> driven by black box <mips_top>. Possible simulation mismatch.
|
|
WARNING:Xst:2036 - Inserting OBUF on port <sys_error<0>> driven by black box <mips_top>. Possible simulation mismatch.
|
|
Building and optimizing final netlist ...
|
|
Changing polarity of register inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10 to handle IOB=TRUE attribute
|
|
INFO:Xst:2261 - The FF/Latch <INT_0> in Unit <mips_sys> is equivalent to the following FF/Latch, which will be removed : <inst_gpio_wb/gpi0_reg_4>
|
|
Found area constraint ratio of 100 (+ 5) on block mips_sys, actual ratio is 19.
|
|
Forward register balancing over carry chain inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/Mcount_count_cy<0>
|
|
Forward register balancing over carry chain inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_v/Mcount_count_cy<0>
|
|
Forward register balancing over carry chain inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_w/Madd_nxtb_addsub0000_cy<0>
|
|
INFO:Xst:2260 - The FF/Latch <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_w/cntg_5> in Unit <mips_sys> is equivalent to the following FF/Latch : <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_w/cntb_5>
|
|
INFO:Xst:2260 - The FF/Latch <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_w/cntg_11> in Unit <mips_sys> is equivalent to the following FF/Latch : <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_w/cntb_11>
|
|
INFO:Xst:2260 - The FF/Latch <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntg_5> in Unit <mips_sys> is equivalent to the following FF/Latch : <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntb_5>
|
|
INFO:Xst:2260 - The FF/Latch <inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/inst_gray_counter_w/cntg_5> in Unit <mips_sys> is equivalent to the following FF/Latch : <inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/inst_gray_counter_w/cntb_5>
|
|
INFO:Xst:2260 - The FF/Latch <inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/inst_gray_counter_w/cntg_5> in Unit <mips_sys> is equivalent to the following FF/Latch : <inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/inst_gray_counter_w/cntb_5>
|
|
INFO:Xst:2260 - The FF/Latch <inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntg_5> in Unit <mips_sys> is equivalent to the following FF/Latch : <inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntb_5>
|
|
INFO:Xst:2260 - The FF/Latch <inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntg_5> in Unit <mips_sys> is equivalent to the following FF/Latch : <inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntb_5>
|
|
INFO:Xst:2260 - The FF/Latch <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntg_11> in Unit <mips_sys> is equivalent to the following FF/Latch : <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntb_11>
|
|
INFO:Xst:2261 - The FF/Latch <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_w/cntg_5> in Unit <mips_sys> is equivalent to the following FF/Latch, which will be removed : <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_w/cntb_5>
|
|
INFO:Xst:2261 - The FF/Latch <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_w/cntg_11> in Unit <mips_sys> is equivalent to the following FF/Latch, which will be removed : <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_w/cntb_11>
|
|
INFO:Xst:2261 - The FF/Latch <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntg_5> in Unit <mips_sys> is equivalent to the following FF/Latch, which will be removed : <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntb_5>
|
|
INFO:Xst:2261 - The FF/Latch <inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/inst_gray_counter_w/cntg_5> in Unit <mips_sys> is equivalent to the following FF/Latch, which will be removed : <inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/inst_gray_counter_w/cntb_5>
|
|
INFO:Xst:2261 - The FF/Latch <inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/inst_gray_counter_w/cntg_5> in Unit <mips_sys> is equivalent to the following FF/Latch, which will be removed : <inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/inst_gray_counter_w/cntb_5>
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INFO:Xst:2261 - The FF/Latch <inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntg_5> in Unit <mips_sys> is equivalent to the following FF/Latch, which will be removed : <inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntb_5>
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INFO:Xst:2261 - The FF/Latch <inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntg_5> in Unit <mips_sys> is equivalent to the following FF/Latch, which will be removed : <inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntb_5>
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INFO:Xst:2261 - The FF/Latch <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntg_11> in Unit <mips_sys> is equivalent to the following FF/Latch, which will be removed : <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntb_11>
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INFO:Xst:2261 - The FF/Latch <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/p10_11> in Unit <mips_sys> is equivalent to the following FF/Latch, which will be removed : <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/p12_11>
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INFO:Xst:2261 - The FF/Latch <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/p11_11> in Unit <mips_sys> is equivalent to the following FF/Latch, which will be removed : <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/p1_11>
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INFO:Xst:2261 - The FF/Latch <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/p20_11> in Unit <mips_sys> is equivalent to the following FF/Latch, which will be removed : <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/p22_11>
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INFO:Xst:2261 - The FF/Latch <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/p21_11> in Unit <mips_sys> is equivalent to the following FF/Latch, which will be removed : <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/p2_11>
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INFO:Xst:2261 - The FF/Latch <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bcnt2_ar_11> in Unit <mips_sys> is equivalent to the following FF/Latch, which will be removed : <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gcnt2_r_11>
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INFO:Xst:2261 - The FF/Latch <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bcnt2_aw_11> in Unit <mips_sys> is equivalent to the following FF/Latch, which will be removed : <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gcnt2_w_11>
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Pipelining and Register Balancing Report ...
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Processing Unit <mips_sys> :
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Register(s) inst_vga_frontend/s_FSM_FFd4 inst_vga_frontend/s_FSM_FFd1 has(ve) been forward balanced into : inst_vga_frontend/s_FSM_Out51_FRB.
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Register(s) inst_ac97_wb/ac_cmd_addr_19 has(ve) been backward balanced into : inst_ac97_wb/ac_cmd_addr_19_BRB0.
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Register(s) inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_19 has(ve) been backward balanced into : inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_19_BRB0 inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_19_BRB1 inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_19_BRB2.
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Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0 has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB1 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB2 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB3.
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Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_1 has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_1_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_1_BRB2 .
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Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_2 has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_2_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_2_BRB2 .
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Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_3 has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_3_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_3_BRB2 .
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Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_4 has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_4_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_4_BRB2 .
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Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_5 has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_5_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_5_BRB2 .
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Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_6 has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_6_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_6_BRB2 .
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Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_7 has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_7_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_7_BRB2 .
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Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_8 has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_8_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_8_BRB2 .
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Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.cas_n has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.cas_n_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.cas_n_BRB1 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.cas_n_BRB2.
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Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.cs_n has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.cs_n_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.cs_n_BRB1 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.cs_n_BRB2 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.cs_n_BRB3.
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Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.ras_n has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.ras_n_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.ras_n_BRB1.
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Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.we_n has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.we_n_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.we_n_BRB1.
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Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntg_3 has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntg_3_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntg_3_BRB1 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntg_3_BRB2.
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Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p1_3 has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p1_3_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p1_3_BRB1 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p1_3_BRB2.
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Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p2_3 has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p2_3_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p2_3_BRB1 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p2_3_BRB2.
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Register(s) inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl/full has(ve) been backward balanced into : inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl/full_BRB0 inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl/full_BRB1 inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl/full_BRB2.
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Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_1 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_1_BRB1 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_1_BRB2.
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Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_10 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_10_BRB1 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_10_BRB2.
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Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_11 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_11_BRB0 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_11_BRB1.
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Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_2 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_2_BRB1 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_2_BRB2.
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Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_3 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_3_BRB1 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_3_BRB2.
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Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_4 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_4_BRB1 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_4_BRB2.
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Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_5 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_5_BRB1 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_5_BRB2.
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Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_6 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_6_BRB1 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_6_BRB2.
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Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_7 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_7_BRB1 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_7_BRB2.
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Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_8 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_8_BRB1 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_8_BRB2.
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Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_9 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_9_BRB1 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_9_BRB2.
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Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_10 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_10_BRB1 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_10_BRB2.
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Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_11 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_11_BRB0 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_11_BRB1.
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Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_5 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_5_BRB1 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_5_BRB2.
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Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_6 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_6_BRB1 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_6_BRB2.
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Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_7 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_7_BRB1 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_7_BRB2.
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Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_8 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_8_BRB1 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_8_BRB2.
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Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_9 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_9_BRB1 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_9_BRB2.
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Register(s) inst_vga_frontend/inst_vga_backend/hsync_r has(ve) been backward balanced into : inst_vga_frontend/inst_vga_backend/hsync_r_BRB0 inst_vga_frontend/inst_vga_backend/hsync_r_BRB1.
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Register(s) inst_vga_frontend/inst_vga_backend/vsync_r has(ve) been backward balanced into : inst_vga_frontend/inst_vga_backend/vsync_r_BRB0.
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Unit <mips_sys> processed.
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Replicating register inst_ps2_wb_1/inst_ps2_core/ps2_clk_tx to handle IOB=TRUE attribute
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Replicating register inst_ps2_wb_0/inst_ps2_core/ps2_data_tx to handle IOB=TRUE attribute
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Replicating register inst_ps2_wb_1/inst_ps2_core/ps2_data_tx to handle IOB=TRUE attribute
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Replicating register inst_ps2_wb_0/inst_ps2_core/ps2_clk_tx to handle IOB=TRUE attribute
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Replicating register inst_ac97_wb/inst_ac_io/inst_ac_out/ac_ssync to handle IOB=TRUE attribute
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Replicating register inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10 to handle IOB=TRUE attribute
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Replicating register inst_usb_port/Mtrien_async_d to handle IOB=TRUE attribute
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Replicating register inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/dqs_zen_0 to handle IOB=TRUE attribute
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Replicating register inst_flash_port/Mtrien_async_d to handle IOB=TRUE attribute
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FlipFlop arb_gnt_0 has been replicated 2 time(s)
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FlipFlop arb_gnt_1 has been replicated 1 time(s)
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FlipFlop inst_clockgen/sys_rst_out has been replicated 14 time(s)
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FlipFlop inst_vga_frontend/s_FSM_FFd2 has been replicated 1 time(s)
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FlipFlop inst_vga_frontend/s_FSM_FFd5 has been replicated 1 time(s)
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FlipFlop inst_vga_frontend/s_FSM_Out51_FRB has been replicated 1 time(s)
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Final Macro Processing ...
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Processing Unit <mips_sys> :
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Found 4-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/u_tag_pipe_4_0>.
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Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/gcnt2_r_0>.
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Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/gcnt2_r_1>.
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Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/gcnt2_r_2>.
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Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/gcnt2_r_4>.
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Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/gcnt2_r_5>.
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Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/gcnt2_w_0>.
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Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/gcnt2_w_1>.
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Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/gcnt2_w_2>.
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Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/gcnt2_w_3>.
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Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/gcnt2_w_4>.
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Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/gcnt2_w_5>.
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Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/gcnt2_w_5>.
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Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/gcnt2_w_4>.
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Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/gcnt2_w_3>.
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Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/gcnt2_w_2>.
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Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/gcnt2_w_1>.
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Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/gcnt2_w_0>.
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Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/gcnt2_r_5>.
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Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/gcnt2_r_4>.
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Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/gcnt2_r_3>.
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Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/gcnt2_r_2>.
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Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/gcnt2_r_1>.
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Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/gcnt2_r_0>.
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Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/gcnt2_w_5>.
|
|
Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/gcnt2_w_4>.
|
|
Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/gcnt2_w_3>.
|
|
Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/gcnt2_w_2>.
|
|
Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/gcnt2_w_1>.
|
|
Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/gcnt2_w_0>.
|
|
Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/gcnt2_r_5>.
|
|
Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/gcnt2_r_4>.
|
|
Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/gcnt2_r_3>.
|
|
Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/gcnt2_r_2>.
|
|
Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/gcnt2_r_1>.
|
|
Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/gcnt2_r_0>.
|
|
Found 20-bit shift register for signal <inst_clockgen/reset_pipe2_19>.
|
|
Found 20-bit shift register for signal <inst_clockgen/reset_pipe1_19>.
|
|
Found 20-bit shift register for signal <inst_clockgen/reset_pipe0_19>.
|
|
Found 6-bit shift register for signal <inst_rom_wb/inst_rom/user_regi_42>.
|
|
Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bcnt2_ar_0>.
|
|
Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bcnt2_ar_1>.
|
|
Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bcnt2_ar_2>.
|
|
Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bcnt2_ar_3>.
|
|
Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bcnt2_ar_4>.
|
|
Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bcnt2_ar_5>.
|
|
Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bcnt2_ar_6>.
|
|
Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bcnt2_ar_7>.
|
|
Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bcnt2_ar_8>.
|
|
Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bcnt2_ar_9>.
|
|
Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bcnt2_ar_10>.
|
|
Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bcnt2_ar_11>.
|
|
Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bcnt2_aw_0>.
|
|
Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bcnt2_aw_1>.
|
|
Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bcnt2_aw_2>.
|
|
Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bcnt2_aw_3>.
|
|
Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bcnt2_aw_4>.
|
|
Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bcnt2_aw_5>.
|
|
Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bcnt2_aw_6>.
|
|
Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bcnt2_aw_7>.
|
|
Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bcnt2_aw_8>.
|
|
Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bcnt2_aw_9>.
|
|
Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bcnt2_aw_10>.
|
|
Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bcnt2_aw_11>.
|
|
Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gcnt2_r_0>.
|
|
Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gcnt2_r_1>.
|
|
Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gcnt2_r_2>.
|
|
Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gcnt2_r_3>.
|
|
Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gcnt2_r_4>.
|
|
Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gcnt2_r_5>.
|
|
Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gcnt2_r_6>.
|
|
Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gcnt2_r_7>.
|
|
Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gcnt2_r_8>.
|
|
Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gcnt2_r_9>.
|
|
Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gcnt2_r_10>.
|
|
Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gcnt2_w_0>.
|
|
Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gcnt2_w_1>.
|
|
Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gcnt2_w_2>.
|
|
Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gcnt2_w_3>.
|
|
Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gcnt2_w_4>.
|
|
Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gcnt2_w_5>.
|
|
Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gcnt2_w_6>.
|
|
Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gcnt2_w_7>.
|
|
Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gcnt2_w_8>.
|
|
Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gcnt2_w_9>.
|
|
Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gcnt2_w_10>.
|
|
Found 3-bit shift register for signal <inst_vga_frontend/inst_char_gen/csr_posy_synced_0>.
|
|
Found 3-bit shift register for signal <inst_vga_frontend/inst_char_gen/csr_posy_synced_1>.
|
|
Found 3-bit shift register for signal <inst_vga_frontend/inst_char_gen/csr_posy_synced_2>.
|
|
Found 3-bit shift register for signal <inst_vga_frontend/inst_char_gen/csr_posy_synced_3>.
|
|
Found 3-bit shift register for signal <inst_vga_frontend/inst_char_gen/csr_posy_synced_4>.
|
|
Found 3-bit shift register for signal <inst_vga_frontend/inst_char_gen/csr_posx_synced_0>.
|
|
Found 3-bit shift register for signal <inst_vga_frontend/inst_char_gen/csr_posx_synced_1>.
|
|
Found 3-bit shift register for signal <inst_vga_frontend/inst_char_gen/csr_posx_synced_2>.
|
|
Found 3-bit shift register for signal <inst_vga_frontend/inst_char_gen/csr_posx_synced_3>.
|
|
Found 3-bit shift register for signal <inst_vga_frontend/inst_char_gen/csr_posx_synced_4>.
|
|
Found 3-bit shift register for signal <inst_vga_frontend/inst_char_gen/csr_posx_synced_5>.
|
|
Found 3-bit shift register for signal <inst_vga_frontend/inst_char_gen/csr_posx_synced_6>.
|
|
Found 2-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p2_3_BRB0>.
|
|
Found 2-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p2_3_BRB1>.
|
|
Found 2-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p2_3_BRB2>.
|
|
Unit <mips_sys> processed.
|
|
|
|
=========================================================================
|
|
Final Register Report
|
|
|
|
Macro Statistics
|
|
# Registers : 3559
|
|
Flip-Flops : 3559
|
|
# Shift Registers : 101
|
|
2-bit shift register : 3
|
|
20-bit shift register : 3
|
|
3-bit shift register : 93
|
|
4-bit shift register : 1
|
|
6-bit shift register : 1
|
|
|
|
=========================================================================
|
|
|
|
=========================================================================
|
|
* Partition Report *
|
|
=========================================================================
|
|
|
|
Partition Implementation Status
|
|
-------------------------------
|
|
|
|
No Partitions were found in this design.
|
|
|
|
-------------------------------
|
|
|
|
=========================================================================
|
|
* Final Report *
|
|
=========================================================================
|
|
Final Results
|
|
RTL Top Level Output File Name : mips_sys.ngr
|
|
Top Level Output File Name : mips_sys
|
|
Output Format : NGC
|
|
Optimization Goal : Speed
|
|
Keep Hierarchy : NO
|
|
|
|
Design Statistics
|
|
# IOs : 226
|
|
|
|
Cell Usage :
|
|
# BELS : 6423
|
|
# GND : 1
|
|
# INV : 93
|
|
# LUT1 : 352
|
|
# LUT2 : 539
|
|
# LUT2_D : 4
|
|
# LUT2_L : 3
|
|
# LUT3 : 1056
|
|
# LUT3_D : 10
|
|
# LUT3_L : 6
|
|
# LUT4 : 2167
|
|
# LUT4_D : 33
|
|
# LUT4_L : 55
|
|
# MULT_AND : 6
|
|
# MUXCY : 1017
|
|
# MUXF5 : 245
|
|
# MUXF6 : 2
|
|
# VCC : 1
|
|
# XORCY : 833
|
|
# FlipFlops/Latches : 3800
|
|
# FD : 318
|
|
# FD_1 : 85
|
|
# FDC : 268
|
|
# FDC_1 : 20
|
|
# FDCE : 255
|
|
# FDCPE : 4
|
|
# FDE : 1373
|
|
# FDP : 78
|
|
# FDPE : 21
|
|
# FDR : 192
|
|
# FDR_1 : 1
|
|
# FDRE : 937
|
|
# FDRS : 58
|
|
# FDRSE : 6
|
|
# FDS : 26
|
|
# FDSE : 84
|
|
# IDDR : 32
|
|
# ODDR : 42
|
|
# RAMS : 127
|
|
# RAM16X1D : 103
|
|
# RAMB16 : 24
|
|
# Shift Registers : 176
|
|
# SRL16 : 100
|
|
# SRL16E : 73
|
|
# SRLC16 : 3
|
|
# Clock Buffers : 12
|
|
# BUFG : 12
|
|
# IO Buffers : 226
|
|
# IBUF : 21
|
|
# IBUFG : 2
|
|
# IOBUF : 84
|
|
# OBUF : 111
|
|
# OBUFT : 8
|
|
# DCM_ADVs : 4
|
|
# DCM_ADV : 4
|
|
# Others : 2
|
|
# BSCAN_VIRTEX4 : 1
|
|
# mips_top : 1
|
|
=========================================================================
|
|
|
|
Device utilization summary:
|
|
---------------------------
|
|
|
|
Selected Device : 4vsx35ff668-10
|
|
|
|
Number of Slices: 2787 out of 15360 18%
|
|
Number of Slice Flip Flops: 3515 out of 30720 11%
|
|
Number of 4 input LUTs: 4700 out of 30720 15%
|
|
Number used as logic: 4318
|
|
Number used as Shift registers: 176
|
|
Number used as RAMs: 206
|
|
Number of IOs: 226
|
|
Number of bonded IOBs: 226 out of 448 50%
|
|
IOB Flip Flops: 285
|
|
Number of FIFO16/RAMB16s: 24 out of 192 12%
|
|
Number used as RAMB16s: 24
|
|
Number of GCLKs: 12 out of 32 37%
|
|
Number of DCM_ADVs: 4 out of 8 50%
|
|
|
|
---------------------------
|
|
Partition Resource Summary:
|
|
---------------------------
|
|
|
|
No Partitions were found in this design.
|
|
|
|
---------------------------
|
|
|
|
|
|
=========================================================================
|
|
TIMING REPORT
|
|
|
|
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
|
|
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
|
|
GENERATED AFTER PLACE-and-ROUTE.
|
|
|
|
Clock Information:
|
|
------------------
|
|
-----------------------------------+---------------------------------------------------------------------------+-------+
|
|
Clock Signal | Clock buffer(FF name) | Load |
|
|
-----------------------------------+---------------------------------------------------------------------------+-------+
|
|
sys_clk_in | inst_clockgen/inst_DCM_SYS_FX:CLKFX | 3392 |
|
|
sys_clk_in | inst_clockgen/inst_DCM_SYS_FX:CLKFX+inst_clockgen/inst_DCM_SDRCLK_0:CLK270| 68 |
|
|
inst_rom_wb/inst_rom/bs_clk0 | BUFG | 98 |
|
|
sys_clk_in | inst_clockgen/inst_DCM_VGA_FX:CLKFX | 252 |
|
|
sys_ac97_bit_clk | IBUF+BUFG | 270 |
|
|
sys_sdr_clk_fb | inst_clockgen/inst_DCM_SDRCLK_1:CLK270 | 32 |
|
|
inst_rom_wb/inst_rom/bs_update0 | BUFG | 4 |
|
|
-----------------------------------+---------------------------------------------------------------------------+-------+
|
|
|
|
Asynchronous Control Signals Information:
|
|
----------------------------------------
|
|
-----------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+-------+
|
|
Control Signal | Buffer(FF name) | Load |
|
|
-----------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+-------+
|
|
RST_O_7(inst_clockgen/sys_rst_out_13:Q) | NONE(inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntb_4)| 289 |
|
|
inst_rom_wb/inst_rom/bs_rst(inst_rom_wb/inst_rom/BSCAN_VIRTEX4_inst1:RESET) | NONE(inst_rom_wb/inst_rom/user_regi_8) | 96 |
|
|
RST_O(inst_clockgen/sys_rst_out:Q) | NONE(inst_ps2_phy_1/Inst_debounce_data/count_2) | 75 |
|
|
inst_ac97_wb/inst_ac_io/ac_reset(inst_ac97_wb/inst_ac_io/ac_reset:Q) | NONE(inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_6) | 52 |
|
|
inst_ac97_wb/tx_fifo_rst(inst_ac97_wb/tx_fifo_rst1:O) | NONE(inst_ac97_wb/inst_tx_fifo/inst_fifo_sync_ctrl/pW_1) | 29 |
|
|
inst_vga_frontend/blit_reset(inst_vga_frontend/blit_reset1:O) | NONE(inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl/pW_5) | 21 |
|
|
inst_clockgen/sdr0_lock_inv(inst_clockgen/sdr0_lock_inv1_INV_0:O) | NONE(inst_clockgen/sdr0_lock_inv_shift1) | 20 |
|
|
inst_clockgen/sys_rst_out_or0000(inst_clockgen/sys_rst_out_or0000:O) | NONE(inst_clockgen/reset_cnt_3) | 20 |
|
|
inst_clockgen/vga_fx_lock_inv(inst_clockgen/vga_fx_lock_inv1_INV_0:O) | NONE(inst_clockgen/vga_fx_lock_inv_shift17) | 20 |
|
|
rst_in(rst_in1:O) | NONE(rst_in_shift2) | 20 |
|
|
inst_ps2_phy_0/Inst_debounce_clk/output_and0000(inst_ps2_phy_0/Inst_debounce_clk/output_and00001:O) | NONE(inst_ps2_phy_0/Inst_debounce_clk/input_last) | 1 |
|
|
inst_ps2_phy_0/Inst_debounce_clk/output_and0001(inst_ps2_phy_0/Inst_debounce_clk/output_and00011:O) | NONE(inst_ps2_phy_0/Inst_debounce_clk/input_last) | 1 |
|
|
inst_ps2_phy_0/Inst_debounce_data/output_and0000(inst_ps2_phy_0/Inst_debounce_data/output_and00001:O)| NONE(inst_ps2_phy_0/Inst_debounce_data/input_last) | 1 |
|
|
inst_ps2_phy_0/Inst_debounce_data/output_and0001(inst_ps2_phy_0/Inst_debounce_data/output_and00011:O)| NONE(inst_ps2_phy_0/Inst_debounce_data/input_last) | 1 |
|
|
inst_ps2_phy_1/Inst_debounce_clk/output_and0000(inst_ps2_phy_1/Inst_debounce_clk/output_and00001:O) | NONE(inst_ps2_phy_1/Inst_debounce_clk/input_last) | 1 |
|
|
inst_ps2_phy_1/Inst_debounce_clk/output_and0001(inst_ps2_phy_1/Inst_debounce_clk/output_and00011:O) | NONE(inst_ps2_phy_1/Inst_debounce_clk/input_last) | 1 |
|
|
inst_ps2_phy_1/Inst_debounce_data/output_and0000(inst_ps2_phy_1/Inst_debounce_data/output_and00001:O)| NONE(inst_ps2_phy_1/Inst_debounce_data/input_last) | 1 |
|
|
inst_ps2_phy_1/Inst_debounce_data/output_and0001(inst_ps2_phy_1/Inst_debounce_data/output_and00011:O)| NONE(inst_ps2_phy_1/Inst_debounce_data/input_last) | 1 |
|
|
-----------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+-------+
|
|
|
|
Timing Summary:
|
|
---------------
|
|
Speed Grade: -10
|
|
|
|
Minimum period: 9.187ns (Maximum Frequency: 108.846MHz)
|
|
Minimum input arrival time before clock: 8.055ns
|
|
Maximum output required time after clock: 10.710ns
|
|
Maximum combinational path delay: 10.288ns
|
|
|
|
Timing Detail:
|
|
--------------
|
|
All values displayed in nanoseconds (ns)
|
|
|
|
=========================================================================
|
|
Timing constraint: Default period analysis for Clock 'sys_clk_in'
|
|
Clock period: 9.187ns (frequency: 108.846MHz)
|
|
Total number of paths / destination ports: 289830 / 8693
|
|
-------------------------------------------------------------------------
|
|
Delay: 2.297ns (Levels of Logic = 0)
|
|
Source: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive (FF)
|
|
Destination: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_32 (FF)
|
|
Source Clock: sys_clk_in falling
|
|
Destination Clock: sys_clk_in rising +270
|
|
|
|
Data Path: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive to inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_32
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
FD_1:C->Q 32 0.307 0.928 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive (inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive)
|
|
FDR:R 1.062 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_32
|
|
----------------------------------------
|
|
Total 2.297ns (1.369ns logic, 0.928ns route)
|
|
(59.6% logic, 40.4% route)
|
|
|
|
=========================================================================
|
|
Timing constraint: Default period analysis for Clock 'inst_rom_wb/inst_rom/bs_clk0'
|
|
Clock period: 2.225ns (frequency: 449.438MHz)
|
|
Total number of paths / destination ports: 97 / 96
|
|
-------------------------------------------------------------------------
|
|
Delay: 2.225ns (Levels of Logic = 0)
|
|
Source: inst_rom_wb/inst_rom/Mshreg_user_regi_42 (FF)
|
|
Destination: inst_rom_wb/inst_rom/user_regi_42 (FF)
|
|
Source Clock: inst_rom_wb/inst_rom/bs_clk0 rising
|
|
Destination Clock: inst_rom_wb/inst_rom/bs_clk0 rising
|
|
|
|
Data Path: inst_rom_wb/inst_rom/Mshreg_user_regi_42 to inst_rom_wb/inst_rom/user_regi_42
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
SRL16E:CLK->Q 1 2.203 0.000 inst_rom_wb/inst_rom/Mshreg_user_regi_42 (inst_rom_wb/inst_rom/Mshreg_user_regi_42)
|
|
FDE:D 0.022 inst_rom_wb/inst_rom/user_regi_42
|
|
----------------------------------------
|
|
Total 2.225ns (2.225ns logic, 0.000ns route)
|
|
(100.0% logic, 0.0% route)
|
|
|
|
=========================================================================
|
|
Timing constraint: Default period analysis for Clock 'sys_ac97_bit_clk'
|
|
Clock period: 5.862ns (frequency: 170.582MHz)
|
|
Total number of paths / destination ports: 3505 / 518
|
|
-------------------------------------------------------------------------
|
|
Delay: 5.862ns (Levels of Logic = 6)
|
|
Source: inst_ac97_wb/inst_ac_io/inst_ac_out/slotcnt_0 (FF)
|
|
Destination: inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_11 (FF)
|
|
Source Clock: sys_ac97_bit_clk rising
|
|
Destination Clock: sys_ac97_bit_clk rising
|
|
|
|
Data Path: inst_ac97_wb/inst_ac_io/inst_ac_out/slotcnt_0 to inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_11
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
FDRE:C->Q 42 0.360 1.295 inst_ac97_wb/inst_ac_io/inst_ac_out/slotcnt_0 (inst_ac97_wb/inst_ac_io/inst_ac_out/slotcnt_0)
|
|
LUT3_D:I0->O 25 0.195 1.228 inst_ac97_wb/inst_ac_io/inst_ac_out/varindex0000_cmp_eq000211 (inst_ac97_wb/inst_ac_io/inst_ac_out/N27)
|
|
LUT4:I1->O 1 0.195 0.741 inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<8>26 (inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<8>26)
|
|
LUT4:I0->O 1 0.195 0.000 inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<8>105_G (N1375)
|
|
MUXF5:I1->O 1 0.374 0.688 inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<8>105 (inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<8>105)
|
|
LUT4:I1->O 1 0.195 0.000 inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<8>1691 (inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<8>169)
|
|
MUXF5:I1->O 1 0.374 0.000 inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<8>169_f5 (inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<8>)
|
|
FDCE:D 0.022 inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_8
|
|
----------------------------------------
|
|
Total 5.862ns (1.910ns logic, 3.952ns route)
|
|
(32.6% logic, 67.4% route)
|
|
|
|
=========================================================================
|
|
Timing constraint: Default OFFSET IN BEFORE for Clock 'sys_clk_in'
|
|
Total number of paths / destination ports: 44049 / 2324
|
|
-------------------------------------------------------------------------
|
|
Offset: 8.055ns (Levels of Logic = 9)
|
|
Source: inst_mips_top:ADDR_O<28> (PAD)
|
|
Destination: inst_vga_frontend/inst_bus_fifo/inst_dpram_1w1r/dout_b_2 (FF)
|
|
Destination Clock: sys_clk_in rising
|
|
|
|
Data Path: inst_mips_top:ADDR_O<28> to inst_vga_frontend/inst_bus_fifo/inst_dpram_1w1r/dout_b_2
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
mips_top:ADDR_O<28> 1 0.000 0.741 inst_mips_top (ADDR_O_cpu<28>)
|
|
LUT4_D:I0->O 5 0.195 0.711 Mmux_ADDR_O211 (ADDR_O<28>)
|
|
LUT4:I1->O 3 0.195 0.600 CYC_I_ac971_SW0 (N403)
|
|
LUT4_D:I2->O 1 0.195 0.523 CYC_I_ac971_1 (CYC_I_ac971)
|
|
LUT3_L:I2->LO 1 0.195 0.225 SRDY_I26_SW0 (N739)
|
|
LUT4:I2->O 1 0.195 0.523 SRDY_I26 (SRDY_I26)
|
|
LUT4_D:I3->LO 1 0.195 0.163 SRDY_I36 (N1558)
|
|
LUT3:I2->O 5 0.195 0.546 inst_vga_frontend/inst_bus_fifo/rinc1 (inst_vga_frontend/inst_bus_fifo/rinc)
|
|
LUT4_D:I3->O 1 0.195 0.523 inst_vga_frontend/inst_bus_fifo/inst_fifo_sync_ctrl/pre_empty_and0000_SW0 (N405)
|
|
LUT3:I2->O 103 0.195 1.205 inst_vga_frontend/inst_bus_fifo/mem_rd_en1 (inst_vga_frontend/inst_bus_fifo/mem_rd_en)
|
|
FDE:CE 0.540 inst_vga_frontend/inst_bus_fifo/inst_dpram_1w1r/dout_b_2
|
|
----------------------------------------
|
|
Total 8.055ns (2.295ns logic, 5.760ns route)
|
|
(28.5% logic, 71.5% route)
|
|
|
|
=========================================================================
|
|
Timing constraint: Default OFFSET IN BEFORE for Clock 'inst_rom_wb/inst_rom/bs_clk0'
|
|
Total number of paths / destination ports: 99 / 99
|
|
-------------------------------------------------------------------------
|
|
Offset: 2.301ns (Levels of Logic = 0)
|
|
Source: inst_rom_wb/inst_rom/BSCAN_VIRTEX4_inst1:SHIFT (PAD)
|
|
Destination: inst_rom_wb/inst_rom/Mshreg_user_regi_42 (FF)
|
|
Destination Clock: inst_rom_wb/inst_rom/bs_clk0 rising
|
|
|
|
Data Path: inst_rom_wb/inst_rom/BSCAN_VIRTEX4_inst1:SHIFT to inst_rom_wb/inst_rom/Mshreg_user_regi_42
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
BSCAN_VIRTEX4:SHIFT 98 0.000 1.186 inst_rom_wb/inst_rom/BSCAN_VIRTEX4_inst1 (inst_rom_wb/inst_rom/bs_shift)
|
|
SRL16E:CE 1.115 inst_rom_wb/inst_rom/Mshreg_user_regi_42
|
|
----------------------------------------
|
|
Total 2.301ns (1.115ns logic, 1.186ns route)
|
|
(48.5% logic, 51.5% route)
|
|
|
|
=========================================================================
|
|
Timing constraint: Default OFFSET IN BEFORE for Clock 'sys_ac97_bit_clk'
|
|
Total number of paths / destination ports: 1 / 1
|
|
-------------------------------------------------------------------------
|
|
Offset: 1.347ns (Levels of Logic = 1)
|
|
Source: sys_ac97_sdata_in (PAD)
|
|
Destination: inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_0 (FF)
|
|
Destination Clock: sys_ac97_bit_clk falling
|
|
|
|
Data Path: sys_ac97_sdata_in to inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_0
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
IBUF:I->O 1 0.965 0.360 sys_ac97_sdata_in_IBUF (sys_ac97_sdata_in_IBUF)
|
|
FDC_1:D 0.022 inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_0
|
|
----------------------------------------
|
|
Total 1.347ns (0.987ns logic, 0.360ns route)
|
|
(73.3% logic, 26.7% route)
|
|
|
|
=========================================================================
|
|
Timing constraint: Default OFFSET IN BEFORE for Clock 'sys_sdr_clk_fb'
|
|
Total number of paths / destination ports: 32 / 32
|
|
-------------------------------------------------------------------------
|
|
Offset: 6.702ns (Levels of Logic = 1)
|
|
Source: sys_sdr_data<31> (PAD)
|
|
Destination: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/gen_ddr_data_in[31].IDDR_data (FF)
|
|
Destination Clock: sys_sdr_clk_fb rising +270
|
|
|
|
Data Path: sys_sdr_data<31> to inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/gen_ddr_data_in[31].IDDR_data
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
IOBUF:IO->O 1 0.965 0.360 sys_sdr_data_31_IOBUF (N407)
|
|
IDDR:D 5.377 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/gen_ddr_data_in[31].IDDR_data
|
|
----------------------------------------
|
|
Total 6.702ns (6.342ns logic, 0.360ns route)
|
|
(94.6% logic, 5.4% route)
|
|
|
|
=========================================================================
|
|
Timing constraint: Default OFFSET IN BEFORE for Clock 'inst_rom_wb/inst_rom/bs_update0'
|
|
Total number of paths / destination ports: 16 / 16
|
|
-------------------------------------------------------------------------
|
|
Offset: 1.341ns (Levels of Logic = 0)
|
|
Source: inst_rom_wb/inst_rom/BSCAN_VIRTEX4_inst1:SEL (PAD)
|
|
Destination: inst_rom_wb/inst_rom/Mram_word_array3 (RAM)
|
|
Destination Clock: inst_rom_wb/inst_rom/bs_update0 rising
|
|
|
|
Data Path: inst_rom_wb/inst_rom/BSCAN_VIRTEX4_inst1:SEL to inst_rom_wb/inst_rom/Mram_word_array3
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
BSCAN_VIRTEX4:SEL 16 0.000 0.593 inst_rom_wb/inst_rom/BSCAN_VIRTEX4_inst1 (inst_rom_wb/inst_rom/bs_sel)
|
|
RAMB16:WEA0 0.748 inst_rom_wb/inst_rom/Mram_word_array3
|
|
----------------------------------------
|
|
Total 1.341ns (0.748ns logic, 0.593ns route)
|
|
(55.8% logic, 44.2% route)
|
|
|
|
=========================================================================
|
|
Timing constraint: Default OFFSET OUT AFTER for Clock 'sys_clk_in'
|
|
Total number of paths / destination ports: 19309 / 226
|
|
-------------------------------------------------------------------------
|
|
Offset: 10.710ns (Levels of Logic = 12)
|
|
Source: inst_vga_frontend/s_FSM_FFd2_1 (FF)
|
|
Destination: inst_mips_top:DAT_I<13> (PAD)
|
|
Source Clock: sys_clk_in rising
|
|
|
|
Data Path: inst_vga_frontend/s_FSM_FFd2_1 to inst_mips_top:DAT_I<13>
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
FDRS:C->Q 1 0.360 0.585 inst_vga_frontend/s_FSM_FFd2_1 (inst_vga_frontend/s_FSM_FFd2_1)
|
|
LUT2_D:I0->O 3 0.195 0.538 inst_vga_frontend/s_FSM_Out61 (inst_vga_frontend/CYC_O_blit_src)
|
|
LUT4_D:I3->LO 1 0.195 0.163 inst_vga_frontend/CYC_O1 (N1553)
|
|
LUT4:I3->O 9 0.195 0.632 CYC_O1 (CYC_O)
|
|
LUT4_D:I3->O 17 0.195 0.743 CYC_I_ac971 (N57)
|
|
LUT4_D:I3->O 48 0.195 1.371 CYC_I_ac972 (CYC_I_ac97)
|
|
LUT4:I0->O 1 0.195 0.741 MDAT_I<13>36_SW0 (N1207)
|
|
LUT4:I0->O 1 0.195 0.585 MDAT_I<13>36 (MDAT_I<13>36)
|
|
LUT4:I2->O 1 0.195 0.741 MDAT_I<13>84_SW0 (N903)
|
|
LUT4:I0->O 1 0.195 0.741 MDAT_I<13>84_SW1 (N1340)
|
|
LUT4:I0->O 1 0.195 0.585 MDAT_I<13>84 (MDAT_I<13>84)
|
|
LUT4:I2->O 1 0.195 0.585 MDAT_I<13>170_SW0 (N875)
|
|
LUT4:I2->O 0 0.195 0.000 MDAT_I<13>170 (MDAT_I<13>)
|
|
mips_top:DAT_I<13> 0.000 inst_mips_top
|
|
----------------------------------------
|
|
Total 10.710ns (2.700ns logic, 8.010ns route)
|
|
(25.2% logic, 74.8% route)
|
|
|
|
=========================================================================
|
|
Timing constraint: Default OFFSET OUT AFTER for Clock 'sys_ac97_bit_clk'
|
|
Total number of paths / destination ports: 2 / 2
|
|
-------------------------------------------------------------------------
|
|
Offset: 4.677ns (Levels of Logic = 1)
|
|
Source: inst_ac97_wb/inst_ac_io/inst_ac_out/ac_sdata_out (FF)
|
|
Destination: sys_ac97_sdata_out (PAD)
|
|
Source Clock: sys_ac97_bit_clk rising
|
|
|
|
Data Path: inst_ac97_wb/inst_ac_io/inst_ac_out/ac_sdata_out to sys_ac97_sdata_out
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
FDC:C->Q 1 0.360 0.360 inst_ac97_wb/inst_ac_io/inst_ac_out/ac_sdata_out (inst_ac97_wb/inst_ac_io/inst_ac_out/ac_sdata_out)
|
|
OBUF:I->O 3.957 sys_ac97_sdata_out_OBUF (sys_ac97_sdata_out)
|
|
----------------------------------------
|
|
Total 4.677ns (4.317ns logic, 0.360ns route)
|
|
(92.3% logic, 7.7% route)
|
|
|
|
=========================================================================
|
|
Timing constraint: Default OFFSET OUT AFTER for Clock 'inst_rom_wb/inst_rom/bs_clk0'
|
|
Total number of paths / destination ports: 1 / 1
|
|
-------------------------------------------------------------------------
|
|
Offset: 0.720ns (Levels of Logic = 0)
|
|
Source: inst_rom_wb/inst_rom/user_rego_0 (FF)
|
|
Destination: inst_rom_wb/inst_rom/BSCAN_VIRTEX4_inst1:TDO (PAD)
|
|
Source Clock: inst_rom_wb/inst_rom/bs_clk0 rising
|
|
|
|
Data Path: inst_rom_wb/inst_rom/user_rego_0 to inst_rom_wb/inst_rom/BSCAN_VIRTEX4_inst1:TDO
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
FDC:C->Q 1 0.360 0.360 inst_rom_wb/inst_rom/user_rego_0 (inst_rom_wb/inst_rom/user_rego_0)
|
|
BSCAN_VIRTEX4:TDO 0.000 inst_rom_wb/inst_rom/BSCAN_VIRTEX4_inst1
|
|
----------------------------------------
|
|
Total 0.720ns (0.360ns logic, 0.360ns route)
|
|
(50.0% logic, 50.0% route)
|
|
|
|
=========================================================================
|
|
Timing constraint: Default path analysis
|
|
Total number of paths / destination ports: 5396 / 38
|
|
-------------------------------------------------------------------------
|
|
Delay: 10.288ns (Levels of Logic = 11)
|
|
Source: inst_mips_top:ADDR_O<28> (PAD)
|
|
Destination: inst_mips_top:DAT_I<13> (PAD)
|
|
|
|
Data Path: inst_mips_top:ADDR_O<28> to inst_mips_top:DAT_I<13>
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
mips_top:ADDR_O<28> 1 0.000 0.741 inst_mips_top (ADDR_O_cpu<28>)
|
|
LUT4_D:I0->O 5 0.195 0.711 Mmux_ADDR_O211 (ADDR_O<28>)
|
|
LUT4:I1->O 3 0.195 0.600 CYC_I_ac971_SW0 (N403)
|
|
LUT4_D:I2->O 17 0.195 0.743 CYC_I_ac971 (N57)
|
|
LUT4_D:I3->O 48 0.195 1.371 CYC_I_ac972 (CYC_I_ac97)
|
|
LUT4:I0->O 1 0.195 0.741 MDAT_I<13>36_SW0 (N1207)
|
|
LUT4:I0->O 1 0.195 0.585 MDAT_I<13>36 (MDAT_I<13>36)
|
|
LUT4:I2->O 1 0.195 0.741 MDAT_I<13>84_SW0 (N903)
|
|
LUT4:I0->O 1 0.195 0.741 MDAT_I<13>84_SW1 (N1340)
|
|
LUT4:I0->O 1 0.195 0.585 MDAT_I<13>84 (MDAT_I<13>84)
|
|
LUT4:I2->O 1 0.195 0.585 MDAT_I<13>170_SW0 (N875)
|
|
LUT4:I2->O 0 0.195 0.000 MDAT_I<13>170 (MDAT_I<13>)
|
|
mips_top:DAT_I<13> 0.000 inst_mips_top
|
|
----------------------------------------
|
|
Total 10.288ns (2.145ns logic, 8.143ns route)
|
|
(20.8% logic, 79.2% route)
|
|
|
|
=========================================================================
|
|
|
|
|
|
Total REAL time to Xst completion: 128.00 secs
|
|
Total CPU time to Xst completion: 128.61 secs
|
|
|
|
-->
|
|
|
|
Total memory usage is 357364 kilobytes
|
|
|
|
Number of errors : 0 ( 0 filtered)
|
|
Number of warnings : 1003 ( 0 filtered)
|
|
Number of infos : 126 ( 0 filtered)
|
|
|