jens
2361b4a440
Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@947 cc03376c-175c-47c8-b038-4cd826a8556b
815 lines
25 KiB
Ruby
815 lines
25 KiB
Ruby
#!/usr/bin/env ruby
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# ----------------------------------------------------------------------
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# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
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# This file: A small assembler for the JCPU
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#
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# Copyright (C) 2007 J. Ahrensfeld
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#
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# This program is free software: you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation, either version 3 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program. If not, see <http://www.gnu.org/licenses/>.
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#
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# For questions and ideas, please contact the author at jens@jayfield.org
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#
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# ---------------------------------------------------------------------
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arg = $*
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FILE_SUFFIX = "jsm"
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IROM_MAX_SIZE = 1024
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IROM_ENTITY_NAME = "irom"
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IROM_DATA_TYPE = "inst_t"
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IROM_ADDR_TYPE = "inst_addr_t"
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XROM_MAX_SIZE = 256
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XROM_DATA_TYPE = "dmem_data_t"
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XROM_ADDR_TYPE = "dmem_addr_t"
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XROM_ENTITY_NAME = "xrom"
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OPC_LIST_NAME = "/cygdrive/w/vhdl/lib/CPUs/JCpu/tools/opc.list"
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# --------------------------------------------------------
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class Parser
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def curr_segment
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@curr_segment
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end
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def curr_segment=(arg)
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@curr_segment=arg
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end
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def add_label(labelname, addr)
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@label_list = @label_list + [labelname, addr]
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end
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def getLabelIdByName(label)
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return @label_list.rindex(label)
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end
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def getLabelNameById(id)
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return @label_list[id]
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end
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def put_instr(name, lc, opc , op1 , op2)
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if get_instr != nil
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STDERR.puts format("Error in line %d: Overlapping sections at %3.3X", lc, @pc)
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exit 1
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end
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@instr_list[@pc] = [lc, @pc, opc , op1 , op2, name]
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end
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def get_instr
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return @instr_list[@pc]
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end
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def put_xmem(value, lc)
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if get_xmem != nil
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STDERR.puts format("Error in line %d: Overlapping sections at %3.3X (%s)", lc, xmem_dc, curr_segment)
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exit 1
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end
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@xmem[xmem_dc] = value
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@xmem_dc = xmem_dc + 1
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end
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def get_xmem
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return @xmem[xmem_dc]
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end
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def xmem
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return @xmem
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end
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def put_cmem(value, lc)
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if get_cmem(page) != nil
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STDERR.puts format("Error in line %d: Overlapping sections at %3.3X (%s)", lc, cmem_dc, curr_segment)
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exit 1
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end
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@cmem[page][cmem_dc] = value
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@cmem_dc[page] = cmem_dc + 1
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end
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def get_cmem(pg)
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return @cmem[pg][cmem_dc]
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end
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def cmem(page)
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return @cmem[page]
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end
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def cmem_dc=(addr)
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@cmem_dc[page] = addr
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end
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def cmem_dc
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@cmem_dc[page]
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end
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def xmem_dc=(addr)
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@xmem_dc = addr
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end
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def xmem_dc
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@xmem_dc
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end
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def page=(page)
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@page = page;
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end
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def page
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@page;
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end
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def pc=(pc)
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@pc = pc;
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if (pc > @pc_max)
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@pc_max = pc
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end
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end
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def pc
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@pc;
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end
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def pc_max
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@pc_max;
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end
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def instr_list
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@instr_list
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end
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def label_list
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@label_list
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end
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def initialize()
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@pc_max = 0
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@pc = 0 # Program counter
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@cmem_dc = [0,0,0,0] # chip data counter
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@xmem_dc = 0 # xmem data counter
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@curr_segment = "UNDEF";
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@page = 0
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@label_list=[[],[]]
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@instr_list=[nil]
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@cmem = [[],[]];
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@xmem = [];
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end
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def method_missing(name, *args)
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puts "I don't know the method #{name}"
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end
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end
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# --------------------------------------------------------
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def parse(name, obj)
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lc = 0 # Line counter
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file = File.open(name, "r")
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file.each do |raw_line|
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lc += 1
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# Make all upper case
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iline = "#{raw_line}".strip
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# Remove comments
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iline = iline.gsub(/;.*/, "")
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# Split instruction at spaces
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iline_member = iline.split(" ")
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if iline_member[0] == nil
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next
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end
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mc = 0;
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label = nil
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clean_line = nil
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if (iline_member[0] =~ /\w+:/)
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mc += 1
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label = iline_member[0].delete(":")
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if obj.getLabelIdByName(label) != nil
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STDERR.puts format("Error in line %d: Duplicate label \"%s\" found", lc, label)
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exit 1
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end
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end
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token = iline_member[mc]
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if token
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token = token.upcase
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end
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case token
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when nil
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if obj.curr_segment == "CMEM"
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curr_addr = format("0x%3.3X",obj.cmem_dc)
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elsif obj.curr_segment == "XMEM"
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curr_addr = format("0x%3.3X",obj.xmem_dc)
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elsif obj.curr_segment == "CODE"
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curr_addr = format("0x%3.3X",obj.pc)
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else
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STDERR.puts format("Error in line %d: Undefined segment", lc)
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exit 1
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end
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when "INCLUDE"
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if iline_member[mc+1] == nil
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STDERR.puts format("Error in line %d: %s needs argument!", lc, token)
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exit 1
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end
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inc_name = iline_member[mc+1].delete("\"")
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puts format("Inserting \"%s\" into \"%s\" at line %d", inc_name, name, lc);
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parse(inc_name, obj)
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when "EQU"
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if iline_member[mc+1] == nil
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STDERR.puts format("Error in line %d: %s needs argument!", lc, token)
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exit 1
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end
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if 0 == (iline_member[mc+1] =~ /\d+/)
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curr_addr = format("0x%2.2X",eval(iline_member[mc+1..iline_member.nitems].to_s))
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else
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curr_addr = iline_member[mc+1]
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end
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when "ORG"
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if iline_member[mc+1] == nil
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STDERR.puts format("Error in line %d: %s needs argument!", lc, token)
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exit 1
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end
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offset = eval(iline_member[mc+1..iline_member.nitems].to_s)
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case obj.curr_segment
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when "CODE"
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obj.pc = offset
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curr_addr = format("0x%3.3X",obj.pc)
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when "CMEM"
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obj.cmem_dc = offset
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when "XMEM"
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obj.xmem_dc = offset
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end
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when "CODE"
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curr_addr = format("0x%3.3X",obj.pc)
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obj.curr_segment = "CODE";
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when "CDATA", "CMEM"
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if iline_member[mc+1] == nil
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STDERR.puts format("Error in line %d: %s needs argument!", lc, token)
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exit 1
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end
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obj.curr_segment = "CMEM";
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obj.page = iline_member[mc+1].to_i(16)
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when "XDATA", "XMEM"
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obj.curr_segment = "XMEM";
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when "DC"
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len = 0;
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if iline_member[mc+1] == nil
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STDERR.puts format("Error in line %d: %s needs argument!", lc, token)
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exit 1
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end
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if obj.curr_segment == "CMEM"
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STDERR.puts format("Error in line %d: %s cannot be initialized!", lc, obj.curr_segment)
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exit 1
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elsif obj.curr_segment == "XMEM"
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curr_addr = format("0x%2.2X",obj.xmem_dc)
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dc_old = obj.xmem_dc;
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val_array = raw_line.split(/dc|DC|Dc|dC/)[1].delete("\t").gsub(/;.*/, "").split(",")
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# Parse string literals
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val_array.each do |item|
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if 0 == (item =~ /.*\".*\"/)
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str = item.delete("\"")
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puts item
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for nn in (0..str.length-1)
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if str[nn] > 31
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obj.put_xmem(str[nn], lc);
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puts "S: " + str[nn].to_s
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len += 1
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end
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end;
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else
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argument = item
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puts "B: " + argument
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obj.put_xmem(eval(argument), lc);
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len += 1
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end
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end
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puts format("Found DC defining %d bytes at 0x%4.4X in %s", len, dc_old, obj.curr_segment);
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else
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STDERR.puts format("Error in line %d: Invalid segment %s for \"%s\"", lc, obj.curr_segment, token)
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exit 1
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end
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when "DB"
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if iline_member[mc+1] == nil
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STDERR.puts format("Error in line %d: %s needs argument!", lc, token)
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exit 1
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end
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len = eval(iline_member[mc+1]).to_i
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if obj.curr_segment == "CMEM"
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curr_addr = format("0x%2.2X",obj.cmem_dc)
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puts format("Found DB reserving %d bytes at 0x%4.4X in %s(%d)", len, obj.cmem_dc, obj.curr_segment, obj.page);
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for nn in (1..len)
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obj.put_cmem(0, lc)
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end
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elsif obj.curr_segment == "XMEM"
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curr_addr = format("0x%2.2X",obj.xmem_dc)
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puts format("Found DB reserving %d bytes at 0x%4.4X in %s", len, obj.xmem_dc, obj.curr_segment);
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for nn in (1..len)
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obj.put_xmem(0, lc)
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end
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else
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STDERR.puts format("Error in line %d: Invalid segment %s for \"%s\"", lc, obj.curr_segment, token)
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exit 1
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end
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else
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if obj.curr_segment != "CODE"
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STDERR.puts format("Error in line %d: Invalid segment %s for \"%s\"", lc, obj.curr_segment, token)
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exit 1
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end
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op_line = iline_member[mc+1..iline_member.nitems].to_s
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curr_addr = format("0x%3.3X",obj.pc)
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opc = token
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if iline_member[mc+1] != nil
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op1 = op_line.gsub(/,+.*$/, "")
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end
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if iline_member[mc+2] != nil
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op2 = op_line.scan(/,.+$/).to_s.delete(", ")
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end
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obj.put_instr(name, lc, opc, op1, op2)
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obj.pc = obj.pc + 1
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end;
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# Push labels
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if label
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obj.add_label(label, curr_addr)
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end
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end
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file.close
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return obj
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end
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# --------------------------------------------------------
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# Instruction formatting
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# --------------------------------------------------------
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def instr(opcode)
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return format("\"%6.6B\" & X\"%3.3X\"",opcode ,0)
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end
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def tcl_bits(pc, opcode)
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return format("%12.12B%8.8B%12.12B",pc, opcode ,0)
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end
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def instr_k(opcode, k)
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return format("\"%6.6B\" & X\"%3.3X\"",opcode ,k)
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end
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def tcl_bits_k(pc, opcode, k)
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return format("%12.12B%8.8B%12.12B",pc, opcode ,k)
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end
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def instr_r(opcode, r)
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return format("\"%6.6B\" & X\"%2.2X%X\"",opcode ,0, r)
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end
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def tcl_bits_r(pc, opcode, r)
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return format("%12.12B%8.8B%8.8B%4.4B",pc, opcode ,0,r)
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end
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def instr_kr(opcode, k, r)
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return format("\"%6.6B\" & X\"%2.2X%X\"",opcode,k, r)
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end
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def tcl_bits_kr(pc, opcode, k, r)
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return format("%12.12B%8.8B%8.8B%4.4B",pc, opcode, k, r)
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end
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def instr_rk(opcode, r, k)
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return format("\"%6.6B\" & X\"%2.2X%X\"",opcode,k, r)
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end
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def tcl_bits_rk(pc, opcode, r, k)
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return format("%12.12B%8.8B%8.8B%4.4B",pc, opcode, k, r)
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end
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def instr_rr(opcode, ra, rb)
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return format("\"%6.6B\" & X\"%X%X%X\"",opcode,0, rb, ra)
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end
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def tcl_bits_rr(pc, opcode, ra, rb)
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return format("%12.12B%8.8B%4.4B%4.4B%4.4B",pc, opcode, 0, rb, ra)
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end
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# --------------------------------------------------------
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# Open file
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# --------------------------------------------------------
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filename = arg.to_s
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if !File.exists?(filename)
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STDERR.puts "#{filename} does not exist"
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exit 1
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end
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PROJECT_NAME = File.basename(filename, "." + FILE_SUFFIX)
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# --------------------------------------------------------
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# Pass 1
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# --------------------------------------------------------
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first_pass = Parser.new();
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parse(filename, first_pass)
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# --------------------------------------------------------
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# Read mnemonic set
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# --------------------------------------------------------
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filename = OPC_LIST_NAME
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if !File.exists?(filename)
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STDERR.puts "#{filename} does not exist"
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exit 1
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end
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mnemo_list = []
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num_opcodes = 0
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file = File.open(filename, "r")
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file.each do |raw_line|
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mnemo_list[num_opcodes] = raw_line.split(" ")[1]
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num_opcodes += 1
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end
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# --------------------------------------------------------
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# Pass 2
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# --------------------------------------------------------
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pc = 0
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opc_start = 2
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num_errors = 0
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vhdl_trans_list = [nil]
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vhdl_comment_list = [nil]
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vhdl_tcl_list = [nil]
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# ToDo: Use class-methods
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label_list = first_pass.label_list
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instr_list = first_pass.instr_list
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instr_list.each do |instruct|
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# puts instruct
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if instruct == nil
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vhdl_trans_list[pc] = format("\"%6.6B\" & X\"%3.3X\"",0 ,0)
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vhdl_comment_list[pc] = format("0x%3.3X:", pc)
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vhdl_tcl_list[pc] = tcl_bits(pc, 0)
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pc += 1
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next
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end
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# determine arglen of instruction
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ilen = 0
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if instruct[opc_start+1] == nil
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arglen = 0
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elsif instruct[opc_start+2] == nil
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arglen = 1
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elsif instruct[opc_start+3] == nil
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arglen = 2
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end
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# Symbol substitution
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error = false
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for i in (1..2)
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subst_pos = opc_start+i
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if instruct[subst_pos] == nil
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next
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end
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expr_token = ""
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expr_subst = nil
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is_direct = true;
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# checks R0 .. R16, Mnemonics
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instruct[subst_pos] = instruct[subst_pos].gsub(/'low/, "")
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if (nil != (instruct[subst_pos] =~ /'high/))
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instruct[subst_pos]= format("%s/256", instruct[subst_pos].gsub(/'high/, ""))
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end
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instr_str = instruct[subst_pos]
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if 0 == (instr_str =~ /\(.+\)/)
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instr_str = instr_str.delete("()")
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is_direct = false;
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end
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expr_token = instr_str.split(/\+|\-|\*|\/|\||\&/)[0]
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if (0 != (expr_token =~ /R[0-9]+/)) && (0 != (expr_token =~ /\d+/))
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idx = label_list.rindex(expr_token)
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if idx != nil
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expr_subst = label_list[idx+1]
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instruct[subst_pos] = instruct[subst_pos].gsub(expr_token, expr_subst)
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else
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STDERR.puts format("%s: Error in line %d: Symbol \"%s\" not found", instruct[5], instruct[0], expr_token)
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error = true
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end
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end
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if expr_subst != nil
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if 0 == (expr_subst =~ /\d+/)
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if is_direct == true
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instruct[subst_pos] = format("0x%2.2X", eval(instruct[subst_pos]))
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else
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instruct[subst_pos] = format("(0x%2.2X)", eval(instruct[subst_pos]))
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end
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else
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if 0 != (expr_subst =~ /R[0-9]+/)
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STDERR.puts format("%s: Error in line %d: Invalid expression \"%s\"", instruct[5], instruct[0], expr_subst)
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error = true
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end
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end
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end
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end
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# Parse operands
|
|
reg = [0,0]
|
|
kk = 0
|
|
format = instruct[opc_start]
|
|
for i in (0..1)
|
|
if instruct[opc_start+i+1] =~ Regexp.new("R[0-9]+")
|
|
# Check indirect addressing
|
|
reg[i] = instruct[opc_start+i+1].delete("R()").to_i
|
|
format += "|R"
|
|
if reg[i] > 15
|
|
STDERR.puts format("%s: Error in line %d: Invalid register \"R%d\" specified", instruct[5], instruct[0], reg[i])
|
|
error = true
|
|
end
|
|
else
|
|
if instruct[opc_start+i+1] =~ Regexp.new("[0-9A-F]+")
|
|
kk = eval(instruct[opc_start+i+1].delete("()"))
|
|
format += "|K"
|
|
end
|
|
end
|
|
if instruct[opc_start+i+1] =~ Regexp.new("\\(.+\\)")
|
|
format += "i";
|
|
end
|
|
end
|
|
|
|
if error
|
|
num_errors += 1
|
|
break
|
|
end
|
|
|
|
# Output instruction
|
|
opcode = mnemo_list.rindex(format).to_i
|
|
mnemo = instruct[2];
|
|
|
|
case format
|
|
# Native instructions
|
|
when "NOP", "HALT", "RET", "RETI", "SETC"
|
|
vhdl_trans_list[pc] = instr(opcode)
|
|
vhdl_tcl_list[pc] = tcl_bits(pc, opcode)
|
|
minstr_comment = format("0x%3.3X: %s", pc, mnemo)
|
|
when "MOVC|R|Ri", "MOVX|R|Ri"
|
|
vhdl_trans_list[pc] = instr_rr(opcode, reg[0], reg[1]);
|
|
vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[0], reg[1])
|
|
minstr_comment = format("0x%3.3X: %s R%2.2d, (R%2.2d)", pc, mnemo, reg[0], reg[1])
|
|
when "MOV|R|R", "SUB|R|R", "SUBC|R|R", "ADD|R|R", "ADDC|R|R", "AND|R|R", "OR|R|R", "XOR|R|R", "CMP|R|R"
|
|
vhdl_trans_list[pc] = instr_rr(opcode, reg[0], reg[1]);
|
|
vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[0], reg[1])
|
|
minstr_comment = format("0x%3.3X: %s R%2.2d, R%2.2d", pc, mnemo, reg[0], reg[1])
|
|
when "MOVC|Ri|R", "MOVX|Ri|R"
|
|
vhdl_trans_list[pc] = instr_rr(opcode, reg[1], reg[0]);
|
|
vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[1], reg[0])
|
|
minstr_comment = format("0x%3.3X: %s (R%2.2d), R%2.2d", pc, mnemo, reg[1], reg[0])
|
|
when "MOVC|Ri|K", "MOVX|Ri|K", "COUT|Ri|K", "XOUT|Ri|K"
|
|
kk = kk % 256;
|
|
vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
|
|
vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
|
|
minstr_comment = format("0x%3.3X: %s (R%2.2d), 0x%2.2X", pc, mnemo, reg[0], kk)
|
|
when "MOVC|R|Ki", "MOVX|R|Ki", "CIN|R|Ki", "XIN|R|Ki"
|
|
vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
|
|
vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
|
|
minstr_comment = format("0x%3.3X: %s R%2.2d, (0x%2.2X)", pc, mnemo, reg[0], kk)
|
|
when "MOV|R|K", "SUB|R|K", "SUBC|R|K", "ADD|R|K", "ADDC|R|K", "AND|R|K", "OR|R|K", "XOR|R|K", "CMP|R|K"
|
|
kk = kk % 256;
|
|
vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
|
|
vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
|
|
minstr_comment = format("0x%3.3X: %s R%2.2d, 0x%2.2X", pc, mnemo, reg[0], kk)
|
|
when "SUB|K|R", "SUBC|K|R"
|
|
kk = kk % 256;
|
|
vhdl_trans_list[pc] = instr_kr(opcode, kk, reg[1]);
|
|
vhdl_tcl_list[pc] = tcl_bits_kr(pc, opcode, kk, reg[1])
|
|
minstr_comment = format("0x%3.3X: %s 0x%2.2d, R%2.2X", pc, mnemo, kk, reg[1])
|
|
when "MOVC|Ki|R", "MOVC|Ki|R", "MOVX|Ki|R", "MOVX|Ki|R", "COUT|Ki|R", "XOUT|Ki|R"
|
|
vhdl_trans_list[pc] = instr_kr(opcode, kk, reg[1]);
|
|
vhdl_tcl_list[pc] = tcl_bits_kr(pc, opcode, kk, reg[1])
|
|
minstr_comment = format("0x%3.3X: %s (0x%2.2X), R%2.2d", pc, mnemo, kk, reg[1])
|
|
when "CALL|K", "JMP|K", "JNZ|K", "JZ|K","JNC|K", "JC|K", "JLT|K", "JGT|K", "JLE|K", "JGE|K", "JEQ|K", "JNE|K"
|
|
vhdl_trans_list[pc] = instr_k(opcode, kk)
|
|
vhdl_tcl_list[pc] = tcl_bits_k(pc, opcode, kk)
|
|
minstr_comment = format("0x%3.3X: %s 0x%3.3X", pc, mnemo, kk)
|
|
when "PUSH|R", "POP|R", "SHR|R", "SHL|R", "ROR|R", "ROL|R", "RORC|R", "ROLC|R", "SWAP|R"
|
|
vhdl_trans_list[pc] = instr_r(opcode, reg[0])
|
|
vhdl_tcl_list[pc] = tcl_bits_r(pc, opcode, reg[0])
|
|
minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
|
|
# Synthetic instructions
|
|
when "CLRC"
|
|
kk = 0;
|
|
minstr_comment = format("0x%3.3X: %s", pc, mnemo)
|
|
opcode = mnemo_list.rindex("SUB|R|K").to_i
|
|
vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
|
|
vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
|
|
when "TST|R"
|
|
kk = 0
|
|
minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
|
|
opcode = mnemo_list.rindex("CMP|R|K").to_i
|
|
vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
|
|
vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
|
|
when "NEG|R"
|
|
kk = 0
|
|
minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
|
|
opcode = mnemo_list.rindex("SUB|K|R").to_i
|
|
vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
|
|
vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
|
|
when "NOT|R"
|
|
kk = 0
|
|
minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
|
|
opcode = mnemo_list.rindex("XOR|R|K").to_i
|
|
vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
|
|
vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
|
|
when "INC|R"
|
|
kk = 1
|
|
minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
|
|
opcode = mnemo_list.rindex("ADD|R|K").to_i
|
|
vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
|
|
vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
|
|
when "DEC|R"
|
|
kk = 1
|
|
minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
|
|
opcode = mnemo_list.rindex("SUB|R|K").to_i
|
|
vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
|
|
vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
|
|
else
|
|
STDERR.puts format("%s: Error in line %d: Not yet implemented %s", instruct[5], instruct[0], format)
|
|
error = true
|
|
end
|
|
|
|
if error
|
|
num_errors += 1
|
|
break
|
|
end
|
|
|
|
vhdl_comment_list[pc] = minstr_comment
|
|
|
|
puts vhdl_trans_list[pc] + " -- " + minstr_comment
|
|
|
|
pc += 1
|
|
end
|
|
|
|
# --------------------------------------------------------
|
|
# Output ROM file
|
|
# --------------------------------------------------------
|
|
if num_errors == 0
|
|
|
|
# I-ROM VHDL-ROM
|
|
filename = format("%s.irom.vhdl.snip", PROJECT_NAME)
|
|
file = File.open(filename, "w")
|
|
|
|
file.puts format("ENTITY %s IS\n", IROM_ENTITY_NAME)
|
|
file.puts format("\tPort (\n")
|
|
file.puts format("\tclk\t\t\t: in STD_LOGIC;\n")
|
|
file.puts format("\tce\t\t\t: in STD_LOGIC;\n")
|
|
file.puts format("\taddr\t\t: in %s;\n", IROM_ADDR_TYPE)
|
|
file.puts format("\tdout\t\t: out %s\n", IROM_DATA_TYPE)
|
|
file.puts format("\t);\n")
|
|
file.puts format("END %s;\n", IROM_ENTITY_NAME)
|
|
file.puts format("\n")
|
|
file.puts format("ARCHITECTURE %s OF %s IS \n", PROJECT_NAME, IROM_ENTITY_NAME)
|
|
file.puts format("\n")
|
|
file.puts format("\ttype imem_rom_t is array (0 to %d) of %s;\n", [IROM_MAX_SIZE, pc].min-1 , IROM_DATA_TYPE)
|
|
file.puts format("\n")
|
|
file.puts format("\t-- Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX)
|
|
file.puts format("\tconstant imem_rom : imem_rom_t :=\n")
|
|
file.puts format("\t(\n");
|
|
for i in (0..[IROM_MAX_SIZE, pc].min-2)
|
|
file.puts "\t\t" + vhdl_trans_list[i] + ", -- " + vhdl_comment_list[i] + "\n"
|
|
end;
|
|
file.puts "\t\t" + vhdl_trans_list[pc-1] + " -- " + vhdl_comment_list[pc-1] + "\n"
|
|
file.puts format("\t);\n")
|
|
file.puts format("\n")
|
|
file.puts format("begin")
|
|
file.puts format("\n")
|
|
file.puts format("PROM_READ:")
|
|
file.puts format("\tprocess(clk, ce)\n")
|
|
file.puts format("\tbegin\n")
|
|
file.puts format("\t\tif rising_edge(clk) and ce = '1' then\n")
|
|
file.puts format("\t\t\tdout <= imem_rom(to_integer(addr));\n")
|
|
file.puts format("\t\tend if;\n")
|
|
file.puts format("\tend process;\n")
|
|
file.puts format("\n")
|
|
file.puts format("end %s;\n", PROJECT_NAME)
|
|
puts format("I-ROM file written to \"%s\"\n",filename)
|
|
file.close
|
|
|
|
# I-ROM VHDL-ROM (loadable)
|
|
filename = format("%s.irom_ld.vhdl.snip", PROJECT_NAME)
|
|
file = File.open(filename, "w")
|
|
|
|
file.puts format("\n\t-- Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX)
|
|
file.puts format("\ttype imem_rom_t is array (0 to %d) of %s;\n", IROM_MAX_SIZE-1, IROM_DATA_TYPE)
|
|
file.puts format("\tsignal imem_rom : imem_rom_t :=\n")
|
|
file.puts format("\t(\n");
|
|
for i in (0..pc-2)
|
|
file.puts "\t\t" + vhdl_trans_list[i] + ", -- " + vhdl_comment_list[i] + "\n"
|
|
end;
|
|
if pc < (IROM_MAX_SIZE-1)
|
|
file.puts "\t\t" + vhdl_trans_list[pc-1] + ", -- " + vhdl_comment_list[pc-1] + "\n"
|
|
for i in (pc..(IROM_MAX_SIZE-2))
|
|
file.puts "\t\t" + instr(0) + ",\n"
|
|
end;
|
|
file.puts "\t\t" + instr(0) + "\n"
|
|
else
|
|
file.puts "\t\t" + vhdl_trans_list[pc-1] + " -- " + vhdl_comment_list[pc-1] + "\n"
|
|
end
|
|
file.puts format("\t);\n")
|
|
puts format("I-ROM (loadable) file written to \"%s\"\n",filename)
|
|
file.close
|
|
|
|
# I-ROM TCL-Loader
|
|
filename = format("%s.irom.tcl.snip", PROJECT_NAME)
|
|
file = File.open(filename, "w")
|
|
file.puts format("# Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX)
|
|
file.puts format("# ---------------------------------------------------------------");
|
|
file.puts format("# Shift the USER1 Instruction (b1111000010) into the Instruction Register of FPGA");
|
|
file.puts format("# User 1")
|
|
file.puts format("set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C2\"]\n\n")
|
|
for i in (0..pc-1)
|
|
# Chipscope 8.1
|
|
# file.puts format("jtag_shiftdr $handle -buffer \"%s\" -endstate RTI -device $devid", vhdl_tcl_list[i].reverse);
|
|
|
|
# Chipscope 9.1
|
|
file.puts format("\# %s", vhdl_comment_list[i])
|
|
file.puts format("::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%8.8X\"\n\n", vhdl_tcl_list[i].length, vhdl_tcl_list[i].to_i(2));
|
|
end;
|
|
puts format("I-ROM TCL-loader written to \"%s\"\n",filename)
|
|
file.close
|
|
|
|
# X-ROM VHDL-ROM
|
|
filename = format("%s.xrom.vhdl.snip", PROJECT_NAME)
|
|
file = File.open(filename, "w")
|
|
|
|
file.puts format("ENTITY %s IS\n", XROM_ENTITY_NAME)
|
|
file.puts format("\tPort (\n")
|
|
file.puts format("\tclk\t\t\t: in STD_LOGIC;\n")
|
|
file.puts format("\tce\t\t\t: in STD_LOGIC;\n")
|
|
file.puts format("\taddr\t\t: in %s;\n", XROM_ADDR_TYPE)
|
|
file.puts format("\tdout\t\t: out %s\n", XROM_DATA_TYPE)
|
|
file.puts format("\t);\n")
|
|
file.puts format("END %s;\n", XROM_ENTITY_NAME)
|
|
file.puts format("\n")
|
|
file.puts format("ARCHITECTURE %s OF %s IS \n", PROJECT_NAME, XROM_ENTITY_NAME)
|
|
file.puts format("\n")
|
|
file.puts format("\ttype xmem_rom_t is array (0 to %d) of %s;\n", XROM_MAX_SIZE-1, XROM_DATA_TYPE)
|
|
file.puts format("\n")
|
|
file.puts format("\t-- Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX)
|
|
file.puts format("\tconstant xmem_rom : xmem_rom_t :=\n")
|
|
file.puts format("\t(\n");
|
|
for i in (0..XROM_MAX_SIZE-2)
|
|
file.puts format("\t\tX\"%2.2X\", -- 0x%2.2X\n", first_pass.xmem[i], i)
|
|
end;
|
|
i = XROM_MAX_SIZE-1
|
|
file.puts format("\t\tX\"%2.2X\" -- 0x%2.2X\n", first_pass.xmem[i], i)
|
|
file.puts format("\t);\n")
|
|
file.puts format("\n")
|
|
file.puts format("begin")
|
|
file.puts format("\n")
|
|
file.puts format("PROM_READ:")
|
|
file.puts format("\tprocess(clk, ce)\n")
|
|
file.puts format("\tbegin\n")
|
|
file.puts format("\t\tif rising_edge(clk) and ce = '1' then\n")
|
|
file.puts format("\t\t\tdout <= xmem_rom(to_integer(addr));\n")
|
|
file.puts format("\t\tend if;\n")
|
|
file.puts format("\tend process;\n")
|
|
file.puts format("\n")
|
|
file.puts format("end %s;\n", PROJECT_NAME)
|
|
puts format("X-ROM file written to \"%s\"\n",filename)
|
|
file.close
|
|
|
|
# X-ROM VHDL-ROM (loadable)
|
|
filename = format("%s.xrom_ld.vhdl.snip", PROJECT_NAME)
|
|
file = File.open(filename, "w")
|
|
|
|
file.puts format("\n\t-- Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX)
|
|
file.puts format("\ttype xmem_rom_t is array (0 to %d) of %s;\n", XROM_MAX_SIZE-1, XROM_DATA_TYPE)
|
|
file.puts format("\tsignal xmem_rom : xmem_rom_t :=\n")
|
|
file.puts format("\t(\n");
|
|
for i in (0..XROM_MAX_SIZE-2)
|
|
file.puts format("\t\tX\"%2.2X\", -- 0x%2.2X\n", first_pass.xmem[i], i)
|
|
end;
|
|
i = XROM_MAX_SIZE-1
|
|
file.puts format("\t\tX\"%2.2X\" -- 0x%2.2X\n", first_pass.xmem[i], i)
|
|
file.puts format("\t);\n")
|
|
puts format("X-ROM (loadable) file written to \"%s\"\n",filename)
|
|
file.close
|
|
|
|
# X-ROM JTAG-Loader
|
|
filename = format("%s.xrom.tcl.snip", PROJECT_NAME)
|
|
file = File.open(filename, "w")
|
|
file.puts format("# Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX)
|
|
file.puts format("# ---------------------------------------------------------------");
|
|
file.puts format("# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA");
|
|
file.puts format("# User 2")
|
|
file.puts format("set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C3\"]\n\n")
|
|
for i in (0..first_pass.xmem.length-1)
|
|
# Chipscope 8.1
|
|
# file.puts format("jtag_shiftdr $handle -buffer \"%s\" -endstate RTI -device $devid", vhdl_tcl_list[i].reverse);
|
|
|
|
# Chipscope 9.1
|
|
file.puts format("::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%2.2X%2.2X\"\n", 16, i, first_pass.xmem[i]);
|
|
end;
|
|
puts format("X-ROM TCL-loader written to \"%s\"\n",filename)
|
|
file.close
|
|
|
|
end
|
|
|
|
# --------------------------------------------------------
|
|
# Output final statistics
|
|
# --------------------------------------------------------
|
|
if num_errors == 0
|
|
puts "Program uses #{first_pass.pc_max} instruction addresses"
|
|
puts "No errors found"
|
|
exit 0
|
|
else
|
|
puts "#{num_errors} errors found"
|
|
exit 1
|
|
end
|
|
|