jens
bdb8fec295
git-svn-id: http://moon:8086/svn/vhdl/trunk@1424 cc03376c-175c-47c8-b038-4cd826a8556b
51 lines
1.6 KiB
VHDL
51 lines
1.6 KiB
VHDL
--------------------------------------------------------------------------
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--
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-- Copyright (C) 1993, Peter J. Ashenden
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-- Mail: Dept. Computer Science
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-- University of Adelaide, SA 5005, Australia
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-- e-mail: petera@cs.adelaide.edu.au
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 1, or (at your option)
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-- any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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--
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--------------------------------------------------------------------------
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--
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-- $RCSfile: clock_gen_test-bench.vhdl,v $ $Revision: 2.1 $ $Date: 1993/10/31 20:29:43 $
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--
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--------------------------------------------------------------------------
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--
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-- Architecture for test bench for clock generator
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--
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architecture bench of clock_gen_test is
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component clock_gen
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port (phi1, phi2 : out bit;
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reset : out bit);
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end component;
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for cg : clock_gen
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use entity work.clock_gen(behaviour)
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generic map (Tpw => 8 ns, Tps => 2 ns);
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signal p1, p2, reset : bit;
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begin
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cg : clock_gen
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port map (p1, p2, reset);
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end bench;
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