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bd1bb90bb0924fddb34a225ce15fe867bf2448bc
vhdl/lib/SDRAM/ddr_sdr_v1_5/sim
T
History
jens bd1bb90bb0 - added Altera/De0-NAno implementation
git-svn-id: http://moon:8086/svn/vhdl/trunk@1256 cc03376c-175c-47c8-b038-4cd826a8556b
2015-05-29 13:15:30 +00:00
..
tb_ctrl_ddr_wb32.fdo
- removed constants from sdram_types.vhd and put them to sdram_const.vhd
2015-05-25 07:25:49 +00:00
tb_ctrl_ddr_wb32.wdo
- update wave
2015-05-24 18:27:52 +00:00
tb_ctrl_ddr_wb64.fdo
- removed constants from sdram_types.vhd and put them to sdram_const.vhd
2015-05-25 07:25:49 +00:00
tb_ctrl_ddr_wb64.wdo
- update wave
2015-05-24 18:27:52 +00:00
tb_ctrl_sdr_wb32_de0nano.fdo
- added Altera/De0-NAno implementation
2015-05-29 13:15:30 +00:00
tb_ctrl_sdr_wb32_de0nano.wdo
- added Altera/De0-NAno implementation
2015-05-29 13:15:30 +00:00
tb_ctrl_sdr_wb32.fdo
[SDRAM CMD FSM]
2015-05-25 09:32:10 +00:00
tb_ctrl_sdr_wb32.wdo
- added Altera/De0-NAno implementation
2015-05-29 13:15:30 +00:00
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