jens
e3aeadebf5
git-svn-id: http://moon:8086/svn/vhdl/trunk@1420 cc03376c-175c-47c8-b038-4cd826a8556b
60 lines
1.3 KiB
VHDL
60 lines
1.3 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 08:22:40 01/17/2009
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-- Design Name:
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-- Module Name: scopetest - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity scopetest is
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Port ( sys_clk : in STD_LOGIC;
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sys_rst_n : in STD_LOGIC;
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clk_out_bus : out STD_LOGIC_VECTOR (7 downto 0);
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clk_out_sma : out STD_LOGIC_VECTOR (3 downto 0)
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);
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end scopetest;
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architecture Behavioral of scopetest is
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signal count : STD_LOGIC_VECTOR (6 downto 0);
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begin
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clk_out_bus <= count & sys_clk;
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clk_out_sma <= count(3 downto 1) & sys_clk;
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process (sys_clk)
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begin
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if sys_clk='1' and sys_clk'event then
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if sys_rst_n='0' then
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count <= (others => '0');
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else
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count <= count + 1;
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end if;
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end if;
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end process;
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end Behavioral;
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