Files
vhdl/projects/dlx/src/test_loop.s
T
jens bdb8fec295 - added
git-svn-id: http://moon:8086/svn/vhdl/trunk@1424 cc03376c-175c-47c8-b038-4cd826a8556b
2021-03-21 11:37:55 +00:00

11 lines
203 B
ArmAsm

.text 0
addi r2, r0, 0 ; r2 := 0
loop:
sw counter(r0), r2 ; counter := r2
addi r2, r2, 1 ; increment r2
snei r1, r2, 10 ; if r2 = 10 then
bnez r1, loop ; next loop
trap 0
counter:
.word 0