jens
b1156e2163
- better BAUD_DIV git-svn-id: http://moon:8086/svn/vhdl/trunk@1345 cc03376c-175c-47c8-b038-4cd826a8556b
145 lines
3.6 KiB
VHDL
145 lines
3.6 KiB
VHDL
-------------------------------------------------------------------------
|
|
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
|
-- This file: cpu_embedded using cpu_core and rom
|
|
--
|
|
-- Copyright (C) 2007 J. Ahrensfeld
|
|
--
|
|
-- This program is free software: you can redistribute it and/or modify
|
|
-- it under the terms of the GNU General Public License as published by
|
|
-- the Free Software Foundation, either version 3 of the License, or
|
|
-- (at your option) any later version.
|
|
--
|
|
-- This program is distributed in the hope that it will be useful,
|
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
-- GNU General Public License for more details.
|
|
--
|
|
-- You should have received a copy of the GNU General Public License
|
|
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
|
--
|
|
-- For questions and ideas, please contact the author at jens@jayfield.org
|
|
--
|
|
--------------------------------------------------------------------------
|
|
|
|
library IEEE;
|
|
use IEEE.STD_LOGIC_1164.ALL;
|
|
use IEEE.numeric_std.ALL;
|
|
|
|
entity tb_juart_tx_rx is
|
|
end;
|
|
|
|
architecture behave of tb_juart_tx_rx is
|
|
|
|
-- Number of user data words for simulation
|
|
constant CLK_PERIOD : time := 10 ns;
|
|
constant BAUD_DIV : natural := 2;
|
|
|
|
-- Common
|
|
signal rst : std_logic := '1';
|
|
signal clk : std_logic := '1';
|
|
signal en_16_x_baud : std_logic := '1';
|
|
|
|
-- TX
|
|
signal send_character : std_logic := '0';
|
|
signal serial_out : std_logic;
|
|
signal Tx_complete : std_logic;
|
|
signal data_in : unsigned(7 downto 0) := (others => '0');
|
|
|
|
-- RX
|
|
signal serial_in : std_logic := '1';
|
|
signal data_strobe : std_logic;
|
|
signal data_out : unsigned(7 downto 0);
|
|
|
|
-- Others
|
|
signal baud_count : unsigned(15 downto 0);
|
|
signal baud_reg : unsigned(15 downto 0) := to_unsigned(BAUD_DIV-1, baud_count'length);
|
|
signal data_rx : unsigned(7 downto 0);
|
|
signal data_tx : unsigned(7 downto 0);
|
|
|
|
begin
|
|
|
|
serial_in <= serial_out;
|
|
|
|
inst_juart_tx : entity work.juart_tx
|
|
PORT MAP
|
|
(
|
|
rst => rst,
|
|
clk => clk,
|
|
en_16_x_baud => en_16_x_baud,
|
|
send_character => send_character,
|
|
Tx_complete => Tx_complete,
|
|
data_in => data_in,
|
|
serial_out => serial_out
|
|
);
|
|
|
|
inst_juart_rx : entity work.juart_rx
|
|
PORT MAP
|
|
(
|
|
rst => rst,
|
|
clk => clk,
|
|
en_16_x_baud => en_16_x_baud,
|
|
data_strobe => data_strobe,
|
|
data_out => data_out,
|
|
serial_in => serial_in
|
|
);
|
|
|
|
CLK_GEN: process
|
|
begin
|
|
wait for CLK_PERIOD/2;
|
|
clk <= not clk;
|
|
end process;
|
|
|
|
PROC_DATAREG_RX: process
|
|
begin
|
|
wait until rising_edge(clk) and data_strobe = '1';
|
|
data_rx <= data_out;
|
|
assert data_out = data_tx report "Data mismatch" severity failure;
|
|
end process;
|
|
|
|
PROC_DATAREG_TX: process
|
|
begin
|
|
wait until rising_edge(clk) and send_character = '1';
|
|
data_tx <= data_in;
|
|
end process;
|
|
|
|
baud_timer:
|
|
process(clk)
|
|
begin
|
|
if rising_edge(clk) then
|
|
en_16_x_baud <= '0';
|
|
if rst = '1' then
|
|
baud_count <= (others => '0');
|
|
elsif baud_count = baud_reg then
|
|
baud_count <= (others => '0');
|
|
en_16_x_baud <= '1';
|
|
else
|
|
baud_count <= baud_count + 1;
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
------------------------------------------------------------------------------------------
|
|
|
|
STIMULUS: process
|
|
|
|
|
|
begin
|
|
|
|
wait for 3*CLK_PERIOD;
|
|
rst <= '0';
|
|
wait for 3*CLK_PERIOD;
|
|
wait until rising_edge(clk);
|
|
|
|
for i in 0 to 255 loop
|
|
wait until rising_edge(clk) and Tx_complete = '1';
|
|
data_in <= to_unsigned(i, 8);
|
|
send_character <= '1';
|
|
wait until rising_edge(clk) and Tx_complete = '0';
|
|
send_character <= '0';
|
|
end loop;
|
|
wait;
|
|
|
|
end process;
|
|
|
|
end architecture behave;
|