jens
67d79572d7
git-svn-id: http://moon:8086/svn/vhdl/trunk@1411 cc03376c-175c-47c8-b038-4cd826a8556b
121 lines
3.1 KiB
VHDL
121 lines
3.1 KiB
VHDL
--------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 17:16:42 13.05.2007
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-- Design Name: tb_nco
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-- Module Name: tb_nco.vhd
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-- Project Name: nco
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.MATH_REAL.ALL;
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USE ieee.numeric_std.ALL;
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use std.textio.all; -- Imports the standard textio package.
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library work;
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use work.fixed_pkg.all;
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use work.nco_pkg.all;
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ENTITY syn_nco IS
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Generic (
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nbits_wave : integer := 18;
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nbits_phase : integer := 16;
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nbits_lut_depth : integer := 12;
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nbits_dither : integer := 4;
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nbits_lfsr : integer := 12;
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q_phase : phase_relation_t := phase_270deg;
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has_pipe_reg : boolean := true;
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has_out_reg : boolean := true
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);
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PORT(
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rst : in std_logic;
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clk : in std_logic;
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pacc_clr : in std_logic;
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pacc_inc : in std_logic;
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freq_in : in unsigned(nbits_phase-1 downto 0);
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freq_load : in std_logic;
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phase_in : in unsigned(nbits_phase-1 downto 0);
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phase_load : in std_logic;
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phase_out : out unsigned(nbits_phase-1 downto 0);
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wave_out_i : out signed(nbits_wave-1 downto 0);
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wave_out_q : out signed(nbits_wave-1 downto 0);
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out_valid : out std_logic
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);
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END syn_nco;
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ARCHITECTURE behavior OF syn_nco IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT nco
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GENERIC (
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nbits_wave : integer;
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nbits_phase : integer;
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nbits_lut_depth : integer;
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nbits_dither : integer;
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nbits_lfsr : integer;
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q_phase : phase_relation_t;
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has_pipe_reg : boolean;
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has_out_reg : boolean
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);
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PORT(
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srst : in std_logic;
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clk : in std_logic;
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pacc_clr : in std_logic;
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pacc_inc : in std_logic;
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freq_in : in unsigned(nbits_phase-1 downto 0);
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freq_load : in std_logic;
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phase_in : in unsigned(nbits_phase-1 downto 0);
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phase_load : in std_logic;
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phase_out : out unsigned(nbits_phase-1 downto 0);
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wave_out_i : out sfixed;
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wave_out_q : out sfixed;
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out_valid : out std_logic
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);
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END COMPONENT;
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--Constants
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constant nbits_wave_frac : integer := nbits_wave;
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--Outputs
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SIGNAL wave_i : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low);
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SIGNAL wave_q : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low);
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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inst_nco: nco
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GENERIC MAP (
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nbits_wave => nbits_wave,
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nbits_phase => nbits_phase,
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nbits_lut_depth => nbits_lut_depth,
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nbits_dither => nbits_dither,
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nbits_lfsr => nbits_lfsr,
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q_phase => q_phase,
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has_pipe_reg => has_pipe_reg,
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has_out_reg => has_out_reg
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)
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PORT MAP(
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srst => rst,
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clk => clk,
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pacc_clr => pacc_clr,
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pacc_inc => pacc_inc,
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freq_in => freq_in,
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freq_load => freq_load,
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phase_in => phase_in,
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phase_load => phase_load,
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phase_out => phase_out,
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wave_out_i => wave_i,
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wave_out_q => wave_q,
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out_valid => out_valid
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);
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wave_out_i <= signed(wave_i);
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wave_out_q <= signed(wave_q);
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END;
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