jens
aef329e702
- registered addr instead of registered output Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@989 cc03376c-175c-47c8-b038-4cd826a8556b
63 lines
1004 B
VHDL
63 lines
1004 B
VHDL
LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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ENTITY rom_wb IS
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Port
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(
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CLK_I : in STD_LOGIC;
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RST_I : in STD_LOGIC;
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CYC_I : in STD_LOGIC;
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WE_I : in STD_LOGIC;
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STB_I : in STD_LOGIC;
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ACK_O : out STD_LOGIC;
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MRDY_I : in STD_LOGIC;
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SRDY_O : out STD_LOGIC;
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ADDR_I : in unsigned(31 downto 0);
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DAT_O : out unsigned(31 downto 0)
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);
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END rom_wb;
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ARCHITECTURE behavior OF rom_wb IS
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COMPONENT rom
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PORT
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(
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clk : in STD_LOGIC;
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ce : in STD_LOGIC;
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addr : in unsigned(31 downto 0);
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dout : out unsigned(31 downto 0)
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);
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END COMPONENT;
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signal data_en : std_logic;
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begin
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data_en <= CYC_I and STB_I and MRDY_I;
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SRDY_O <= CYC_I;
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data_valid_register:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if RST_I = '1' then
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ACK_O <= '0';
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else
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ACK_O <= data_en and not WE_I;
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end if;
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end if;
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end process;
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inst_rom : rom
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PORT MAP
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(
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clk => CLK_I,
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ce => data_en,
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addr => ADDR_I,
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dout => DAT_O
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);
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end behavior;
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