jens
ac38fe2513
git-svn-id: http://moon:8086/svn/vhdl/trunk@1141 cc03376c-175c-47c8-b038-4cd826a8556b
630 lines
21 KiB
Plaintext
630 lines
21 KiB
Plaintext
#
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# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
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# SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
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# XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
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# AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
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# OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
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# IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
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# AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
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# FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
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# WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
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# IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
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# REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
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# INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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# FOR A PARTICULAR PURPOSE.
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#
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# (c) Copyright 2005 Xilinx, Inc.
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# All rights reserved.
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#
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CONFIG STEPPING = "ES";
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# Bus clock nets
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NET "CLK_O" TNM_NET = "sys_clk";
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TIMESPEC "TS_clk" = PERIOD "sys_clk" 9.9 ns HIGH 50 %;
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NET "sdram_clk0" TNM_NET = "sdram_clk";
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TIMESPEC "TS_sdram_clk" = PERIOD "sdram_clk" 7.5 ns HIGH 50 %;
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TIMESPEC "TS_unrelate_SDRAM" = FROM sys_clk TO sdram_clk TIG;
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NET "vga_clk" TNM_NET = "vga_clk";
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TIMESPEC "TS_vga_clk" = PERIOD "vga_clk" 8.0 ns HIGH 50 %;
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TIMESPEC "TS_unrelate_VGA" = FROM sys_clk TO vga_clk TIG;
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NET "cpu_clk" TNM_NET = "cpu_clk";
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TIMESPEC "TS_cpu_clk" = PERIOD "cpu_clk" 9.9 ns HIGH 50 %;
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#TIMESPEC "TS_unrelate_CPU" = FROM sys_clk TO cpu_clk TIG;
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NET "sys_clk_in" LOC = "AE14";
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NET sys_clk_in IOSTANDARD = LVCMOS33;
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NET "sys_rst_n_in" LOC = "D6";
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NET sys_rst_n_in PULLUP;
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NET "sys_rst_n_in" TIG;
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NET "RST_O" TIG;
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#NET "sys_clk_in" CLOCK_DEDICATED_ROUTE = FALSE;
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#PIN "inst_clockgen/inst_DCM_BASE_0.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE;
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#NET "sys_sdr_clk_fb" CLOCK_DEDICATED_ROUTE = FALSE;
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#PIN "inst_clockgen/inst_DCM_BASE_0.CLKFB" CLOCK_DEDICATED_ROUTE = FALSE;
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# Locate DCM/BUFG - Tools can probably figure them out automatically
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# but just LOC them down to be safe
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#INST inst_clockgen/inst_DCM_BASE_0 LOC = DCM_ADV_X0Y4;
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#INST inst_clockgen/inst_DCM_BASE_1 LOC = DCM_ADV_X0Y3;
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# ---------------------------------------------------------------------------------
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# Floor planning
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# ---------------------------------------------------------------------------------
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#INST "inst_vga_frontend" AREA_GROUP = "AG_inst_vga_frontend" ;
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#AREA_GROUP "AG_inst_vga_frontend" RANGE = SLICE_X8Y191:SLICE_X30Y141 ;
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#AREA_GROUP "AG_inst_vga_frontend" RANGE = RAMB16_X0Y18:RAMB16_X0Y23, RAMB16_X1Y18:RAMB16_X1Y23, RAMB16_X2Y18:RAMB16_X2Y23 ;
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#INST "inst_sdram_ctrl_frontend_wb" AREA_GROUP = "AG_inst_sdram_ctrl_frontend_wb" ;
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#AREA_GROUP "AG_inst_sdram_ctrl_frontend_wb" RANGE = SLICE_X0Y191:SLICE_X7Y141 ;
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INST "inst_mips_top" AREA_GROUP = "AG_inst_mips_top" ;
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# GOOD 1
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#AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y85:SLICE_X39Y0 ;
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#AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y10, RAMB16_X1Y0:RAMB16_X1Y10, RAMB16_X2Y0:RAMB16_X2Y10, RAMB16_X3Y0:RAMB16_X3Y10 ;
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# GOOD 2 (smaller)
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#AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y69:SLICE_X39Y0 ;
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#AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y8, RAMB16_X1Y0:RAMB16_X1Y8, RAMB16_X2Y0:RAMB16_X2Y8, RAMB16_X3Y0:RAMB16_X3Y8 ;
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# GOOD 3 (even smaller)
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#AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y61:SLICE_X39Y0 ;
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#AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y7, RAMB16_X1Y0:RAMB16_X1Y7, RAMB16_X2Y0:RAMB16_X2Y7, RAMB16_X3Y0:RAMB16_X3Y7 ;
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# GOOD 4 (even more smaller)
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AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y53:SLICE_X39Y0 ;
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AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y6, RAMB16_X1Y0:RAMB16_X1Y6, RAMB16_X2Y0:RAMB16_X2Y6, RAMB16_X3Y0:RAMB16_X3Y6 ;
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# TEMP 4
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#AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y54:SLICE_X39Y0 ;
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#AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y6, RAMB16_X1Y0:RAMB16_X1Y6, RAMB16_X2Y0:RAMB16_X2Y6, RAMB16_X3Y0:RAMB16_X3Y6 ;
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# TEMP 4.1
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#AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y55:SLICE_X39Y0 ;
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#AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y6, RAMB16_X1Y0:RAMB16_X1Y6, RAMB16_X2Y0:RAMB16_X2Y6, RAMB16_X3Y0:RAMB16_X3Y6 ;
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////////////////////////////////////////////////////////////////////////////
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// Misc Board Signals
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////////////////////////////////////////////////////////////////////////////
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NET sys_error<0> LOC = V6;
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NET sys_error<1> LOC = L24;
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NET sys_error<*> IOSTANDARD = LVCMOS33;
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NET sys_error<*> DRIVE = 2;
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NET sys_error<*> TIG;
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////////////////////////////////////////////////////////////////////////////
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// RS-232
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////////////////////////////////////////////////////////////////////////////
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NET sys_uart0_rx LOC = W2;
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NET sys_uart0_rx IOSTANDARD = LVCMOS33;
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NET sys_uart0_rx TIG;
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NET sys_uart0_tx LOC = W1;
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NET sys_uart0_tx IOSTANDARD = LVCMOS33;
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NET sys_uart0_tx TIG;
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NET sys_uart1_rx LOC = AF24;
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NET sys_uart1_rx IOSTANDARD = LVCMOS33;
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NET sys_uart1_rx TIG;
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NET sys_uart1_tx LOC = AE24;
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NET sys_uart1_tx IOSTANDARD = LVCMOS33;
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NET sys_uart1_tx TIG;
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NET sys_uart2_rx LOC = AD22;
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NET sys_uart2_rx IOSTANDARD = LVCMOS33;
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NET sys_uart2_rx TIG;
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NET sys_uart2_tx LOC = AB21;
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NET sys_uart2_tx IOSTANDARD = LVCMOS33;
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NET sys_uart2_tx TIG;
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NET sys_uart3_rx LOC = W20;
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NET sys_uart3_rx IOSTANDARD = LVCMOS33;
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NET sys_uart3_rx TIG;
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NET sys_uart3_tx LOC = W21;
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NET sys_uart3_tx IOSTANDARD = LVCMOS33;
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NET sys_uart3_tx TIG;
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////////////////////////////////////////////////////////////////////////////
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// Buttons, LEDs, and DIP Switches
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////////////////////////////////////////////////////////////////////////////
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# GPLED 0-3
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NET "sys_led<0>" LOC = "G5"; #GPLED0
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NET "sys_led<1>" LOC = "G6"; #GPLED1
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NET "sys_led<2>" LOC = "A11"; #GPLED2
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NET "sys_led<3>" LOC = "A12"; #GPLED3
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# North-East-South-West-Center LEDs
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NET "sys_led<4>" LOC = "F9"; # W LED
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NET "sys_led<5>" LOC = "E2"; # N LED
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NET "sys_led<6>" LOC = "E10"; # E LED
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NET "sys_led<7>" LOC = "A5"; # S LED
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NET "sys_led<8>" LOC = "C6"; # C LED
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NET "sys_led<*>" TIG;
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NET "sys_led<*>" SLEW = SLOW;
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NET "sys_led<*>" DRIVE = 2;
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#NET "sys_led<*>" IOSTANDARD = LVCMOS33;
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# North-East-South-West-Center Buttons
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NET "sys_btn<0>" LOC = "E9"; # W Button
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NET "sys_btn<1>" LOC = "E7"; # N Button
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NET "sys_btn<2>" LOC = "F10"; # E Button
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NET "sys_btn<3>" LOC = "A6"; # S Button
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NET "sys_btn<4>" LOC = "B6"; # C Button
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NET "sys_btn<*>" TIG;
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NET "sys_btn<*>" PULLDOWN;
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#NET "sys_btn<*>" IOSTANDARD = LVCMOS33;
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# Dip Switches 1-8
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NET "sys_dip<7>" LOC = "U24"; # DIP SW 8
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NET "sys_dip<6>" LOC = "U25"; # DIP SW 7
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NET "sys_dip<5>" LOC = "V23"; # DIP SW 6
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NET "sys_dip<4>" LOC = "U23"; # DIP SW 5
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NET "sys_dip<3>" LOC = "U26"; # DIP SW 4
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NET "sys_dip<2>" LOC = "T26"; # DIP SW 3
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NET "sys_dip<1>" LOC = "R19"; # DIP SW 2
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NET "sys_dip<0>" LOC = "R20"; # DIP SW 1
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NET "sys_dip<*>" PULLDOWN;
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NET "sys_dip<*>" IOSTANDARD = LVCMOS33;
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NET "sys_dip<*>" TIG;
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////////////////////////////////////////////////////////////////////////////
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// LCD
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////////////////////////////////////////////////////////////////////////////
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NET sys_lcd_e LOC = AE13; # LCD_E
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NET sys_lcd_e IOSTANDARD = LVCMOS33;
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NET sys_lcd_e SLEW = SLOW;
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NET sys_lcd_e DRIVE = 2;
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NET sys_lcd_e TIG;
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NET sys_lcd_rs LOC = AC17; # LCD_RS
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NET sys_lcd_rs IOSTANDARD = LVCMOS33;
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NET sys_lcd_rs SLEW = SLOW;
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NET sys_lcd_rs DRIVE = 2;
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NET sys_lcd_rs TIG;
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NET sys_lcd_rw LOC = AB17; # LCD_RW
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NET sys_lcd_rw IOSTANDARD = LVCMOS33;
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NET sys_lcd_rw SLEW = SLOW;
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NET sys_lcd_rw DRIVE = 2;
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NET sys_lcd_rw TIG;
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NET sys_lcd_d<3> LOC = AF12; # LCD_DB7
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NET sys_lcd_d<2> LOC = AE12; # LCD_DB6
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NET sys_lcd_d<1> LOC = AC10; # LCD_DB5
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NET sys_lcd_d<0> LOC = AB10; # LCD_DB4
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NET sys_lcd_d<*> IOSTANDARD = LVCMOS33;
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NET sys_lcd_d<*> SLEW = SLOW;
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NET sys_lcd_d<*> DRIVE = 2;
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NET sys_lcd_d<*> PULLDOWN;
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NET sys_lcd_d<*> TIG;
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#------------------------------------------------------------------------------
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# IO Pad Location Constraints / Properties for DDR Controllers
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#------------------------------------------------------------------------------
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NET sys_sdr_a_q<0> LOC = C26; # DDR_A0
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NET sys_sdr_a_q<1> LOC = E17; # DDR_A1
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NET sys_sdr_a_q<2> LOC = D18; # DDR_A2
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NET sys_sdr_a_q<3> LOC = C19; # DDR_A3
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NET sys_sdr_a_q<4> LOC = F17; # DDR_A4
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NET sys_sdr_a_q<5> LOC = B18; # DDR_A5
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NET sys_sdr_a_q<6> LOC = B20; # DDR_A6
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NET sys_sdr_a_q<7> LOC = C20; # DDR_A7
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NET sys_sdr_a_q<8> LOC = D20; # DDR_A8
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NET sys_sdr_a_q<9> LOC = C21; # DDR_A9
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NET sys_sdr_a_q<10> LOC = A18; # DDR_A10
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NET sys_sdr_a_q<11> LOC = B21; # DDR_A11
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NET sys_sdr_a_q<12> LOC = A24; # DDR_A12
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NET sys_sdr_ba_q<0> LOC = B12; # DDR_BA0
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NET sys_sdr_ba_q<1> LOC = A16; # DDR_BA1
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NET sys_sdr_cas_qn LOC = F23; # DDR_CAS_N
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NET sys_sdr_cke_q LOC = G22; # DDR_CKE
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NET sys_sdr_cs_qn LOC = G21; # DDR_CS_N
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NET sys_sdr_ras_qn LOC = F24; # DDR_RAS_N
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NET sys_sdr_we_qn LOC = A23; # DDR_WE_N
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NET sys_sdr_clk_p LOC = A10; # DDR_CK1_P
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NET sys_sdr_clk_fb LOC = B13; # DDR_CK1_P (FEEDBACK)
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NET sys_sdr_clk_n LOC = B10; # DDR_CK1_N
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NET sys_sdr_dm_q<0> LOC = G19; # DDR_DM0
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NET sys_sdr_dm_q<1> LOC = G24; # DDR_DM1
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NET sys_sdr_dm_q<2> LOC = G20; # DDR_DM2
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NET sys_sdr_dm_q<3> LOC = C22; # DDR_DM3
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NET sys_sdr_dqs_q<0> LOC = D25; # DDR_DQS0
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NET sys_sdr_dqs_q<1> LOC = G18; # DDR_DQS1
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NET sys_sdr_dqs_q<2> LOC = G17; # DDR_DQS2
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NET sys_sdr_dqs_q<3> LOC = D26; # DDR_DQS3
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NET sys_sdr_data<0> LOC = H20; # DDR_D0
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NET sys_sdr_data<1> LOC = E23; # DDR_D1
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NET sys_sdr_data<2> LOC = H26; # DDR_D2
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NET sys_sdr_data<3> LOC = H22; # DDR_D3
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NET sys_sdr_data<4> LOC = E25; # DDR_D4
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NET sys_sdr_data<5> LOC = E26; # DDR_D5
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NET sys_sdr_data<6> LOC = F26; # DDR_D6
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NET sys_sdr_data<7> LOC = E24; # DDR_D7
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NET sys_sdr_data<8> LOC = E20; # DDR_D8
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NET sys_sdr_data<9> LOC = A22; # DDR_D9
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NET sys_sdr_data<10> LOC = C23; # DDR_D10
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NET sys_sdr_data<11> LOC = C24; # DDR_D11
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NET sys_sdr_data<12> LOC = A20; # DDR_D12
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NET sys_sdr_data<13> LOC = A21; # DDR_D13
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NET sys_sdr_data<14> LOC = D24; # DDR_D14
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NET sys_sdr_data<15> LOC = E18; # DDR_D15
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NET sys_sdr_data<16> LOC = F18; # DDR_D16
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NET sys_sdr_data<17> LOC = A19; # DDR_D17
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NET sys_sdr_data<18> LOC = F19; # DDR_D18
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NET sys_sdr_data<19> LOC = B23; # DDR_D19
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NET sys_sdr_data<20> LOC = E21; # DDR_D20
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NET sys_sdr_data<21> LOC = D22; # DDR_D21
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NET sys_sdr_data<22> LOC = D23; # DDR_D22
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NET sys_sdr_data<23> LOC = B24; # DDR_D23
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NET sys_sdr_data<24> LOC = E22; # DDR_D24
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NET sys_sdr_data<25> LOC = F20; # DDR_D25
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NET sys_sdr_data<26> LOC = H23; # DDR_D26
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NET sys_sdr_data<27> LOC = G25; # DDR_D27
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NET sys_sdr_data<28> LOC = G26; # DDR_D28
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NET sys_sdr_data<29> LOC = H25; # DDR_D29
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NET sys_sdr_data<30> LOC = H24; # DDR_D30
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NET sys_sdr_data<31> LOC = H21; # DDR_D31
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NET sys_sdr_a_q<*> IOSTANDARD = SSTL2_I;
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NET sys_sdr_a_q<*> FAST;
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NET sys_sdr_ba_q<*> IOSTANDARD = SSTL2_I;
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NET sys_sdr_ba_q<*> FAST;
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NET sys_sdr_cas_qn IOSTANDARD = SSTL2_I;
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NET sys_sdr_cas_qn FAST;
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NET sys_sdr_cke_q IOSTANDARD = SSTL2_I;
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NET sys_sdr_cke_q FAST;
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NET sys_sdr_clk_p IOSTANDARD = SSTL2_I;
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NET sys_sdr_clk_p FAST;
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NET sys_sdr_clk_fb IOSTANDARD = LVCMOS25;
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NET sys_sdr_clk_fb IOBDELAY = NONE;
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NET sys_sdr_clk_n IOSTANDARD = SSTL2_I;
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NET sys_sdr_clk_n FAST;
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NET sys_sdr_cs_qn IOSTANDARD = SSTL2_I;
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NET sys_sdr_cs_qn FAST;
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NET sys_sdr_ras_qn IOSTANDARD = SSTL2_I;
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NET sys_sdr_ras_qn FAST;
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NET sys_sdr_we_qn IOSTANDARD = SSTL2_I;
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NET sys_sdr_we_qn FAST;
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NET sys_sdr_dqs_q<*> IOSTANDARD = SSTL2_II;
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NET sys_sdr_dqs_q<*> IOBDELAY = NONE;
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NET sys_sdr_dqs_q<*> FAST;
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NET sys_sdr_dm_q<*> IOSTANDARD = SSTL2_II;
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NET sys_sdr_dm_q<*> IOBDELAY = NONE;
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NET sys_sdr_dm_q<*> FAST;
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NET sys_sdr_data<*> IOSTANDARD = SSTL2_II;
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NET sys_sdr_data<*> IOBDELAY = NONE;
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NET sys_sdr_data<*> FAST;
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#NET "sys_sdr_data<*>" OFFSET=OUT 2.5 ns BEFORE "sys_sdr_clk_n";
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NET "sys_sdr_clk_p" TNM_NET = "ddr_clk_p";
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NET "sys_sdr_clk_n" TNM_NET = "ddr_clk_n";
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# Timing Constraint for DDR Feedback Clock
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NET sys_sdr_clk_fb FEEDBACK = 1 ns NET sys_sdr_clk_p;
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# USB
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NET sys_usb_a<0> LOC = Y10;
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NET sys_usb_a<1> LOC = AA10;
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NET sys_usb_a<*> IOSTANDARD = LVCMOS33;
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NET sys_usb_d<0> LOC = AB7;
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NET sys_usb_d<1> LOC = AC9;
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NET sys_usb_d<2> LOC = AB9;
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NET sys_usb_d<3> LOC = AE6;
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NET sys_usb_d<4> LOC = AD6;
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NET sys_usb_d<5> LOC = AF9;
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NET sys_usb_d<6> LOC = AE9;
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NET sys_usb_d<7> LOC = AD8;
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NET sys_usb_d<8> LOC = AC8;
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NET sys_usb_d<9> LOC = AF4;
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NET sys_usb_d<10> LOC = AE4;
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NET sys_usb_d<11> LOC = AD3;
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NET sys_usb_d<12> LOC = AC3;
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NET sys_usb_d<13> LOC = AF6;
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NET sys_usb_d<14> LOC = AF5;
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NET sys_usb_d<15> LOC = AA7;
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NET sys_usb_d<*> IOSTANDARD = LVCMOS33;
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NET sys_usb_d<*> SLEW = FAST;
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NET sys_usb_d<*> DRIVE = 8;
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NET sys_usb_d<*> PULLDOWN;
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NET sys_usb_d<*> IOBDELAY = NONE;
|
|
|
|
NET sys_usb_rdn LOC = AA8;
|
|
NET sys_usb_rdn IOSTANDARD = LVCMOS33;
|
|
NET sys_usb_rdn SLEW = FAST;
|
|
NET sys_usb_rdn DRIVE = 8;
|
|
|
|
NET sys_usb_wrn LOC = Y8;
|
|
NET sys_usb_wrn IOSTANDARD = LVCMOS33;
|
|
NET sys_usb_wrn SLEW = FAST;
|
|
NET sys_usb_wrn DRIVE = 8;
|
|
|
|
NET sys_usb_csn LOC = AF10;
|
|
NET sys_usb_csn IOSTANDARD = LVCMOS33;
|
|
NET sys_usb_csn SLEW = FAST;
|
|
NET sys_usb_csn DRIVE = 8;
|
|
|
|
NET sys_usb_rstn LOC = A7;
|
|
NET sys_usb_rstn IOSTANDARD = LVCMOS25;
|
|
NET sys_usb_rstn TIG;
|
|
|
|
NET sys_usb_int LOC = V5;
|
|
NET sys_usb_int IOSTANDARD = LVCMOS33;
|
|
NET sys_usb_int PULLDOWN;
|
|
NET sys_usb_int TIG;
|
|
|
|
# FLASH
|
|
NET sys_flash_a<24> LOC = T21;
|
|
NET sys_flash_a<23> LOC = U20;
|
|
NET sys_flash_a<22> LOC = T19;
|
|
NET sys_flash_a<21> LOC = AC5;
|
|
NET sys_flash_a<20> LOC = AB5;
|
|
NET sys_flash_a<19> LOC = AC4;
|
|
NET sys_flash_a<18> LOC = AB4;
|
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NET sys_flash_a<17> LOC = AB3;
|
|
NET sys_flash_a<16> LOC = AA4;
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|
NET sys_flash_a<15> LOC = AA3;
|
|
NET sys_flash_a<14> LOC = W5;
|
|
NET sys_flash_a<13> LOC = W6;
|
|
NET sys_flash_a<12> LOC = W3;
|
|
NET sys_flash_a<11> LOC = AF3;
|
|
NET sys_flash_a<10> LOC = AE3;
|
|
NET sys_flash_a<9> LOC = AD2;
|
|
NET sys_flash_a<8> LOC = AD1;
|
|
NET sys_flash_a<7> LOC = AC2;
|
|
NET sys_flash_a<6> LOC = AC1;
|
|
NET sys_flash_a<5> LOC = AB2;
|
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NET sys_flash_a<4> LOC = AB1;
|
|
NET sys_flash_a<3> LOC = AA1;
|
|
NET sys_flash_a<2> LOC = Y2;
|
|
NET sys_flash_a<1> LOC = Y1;
|
|
NET sys_flash_a<0> LOC = T20;
|
|
|
|
NET sys_flash_d<31> LOC = F14;
|
|
NET sys_flash_d<30> LOC = F13;
|
|
NET sys_flash_d<29> LOC = F12;
|
|
NET sys_flash_d<28> LOC = F11;
|
|
NET sys_flash_d<27> LOC = F16;
|
|
NET sys_flash_d<26> LOC = F15;
|
|
NET sys_flash_d<25> LOC = D14;
|
|
NET sys_flash_d<24> LOC = D13;
|
|
NET sys_flash_d<23> LOC = D15;
|
|
NET sys_flash_d<22> LOC = E14;
|
|
NET sys_flash_d<21> LOC = C11;
|
|
NET sys_flash_d<20> LOC = D11;
|
|
NET sys_flash_d<19> LOC = D16;
|
|
NET sys_flash_d<18> LOC = C16;
|
|
NET sys_flash_d<17> LOC = E13;
|
|
NET sys_flash_d<16> LOC = D12;
|
|
NET sys_flash_d<15> LOC = AA14;
|
|
NET sys_flash_d<14> LOC = AB14;
|
|
NET sys_flash_d<13> LOC = AC12;
|
|
NET sys_flash_d<12> LOC = AC11;
|
|
NET sys_flash_d<11> LOC = AA16;
|
|
NET sys_flash_d<10> LOC = AA15;
|
|
NET sys_flash_d<9> LOC = AB13;
|
|
NET sys_flash_d<8> LOC = AA13;
|
|
NET sys_flash_d<7> LOC = AC14;
|
|
NET sys_flash_d<6> LOC = AD14;
|
|
NET sys_flash_d<5> LOC = AA12;
|
|
NET sys_flash_d<4> LOC = AA11;
|
|
NET sys_flash_d<3> LOC = AC16;
|
|
NET sys_flash_d<2> LOC = AC15;
|
|
NET sys_flash_d<1> LOC = AC13;
|
|
NET sys_flash_d<0> LOC = AD13;
|
|
NET sys_flash_rdn LOC = AC6;
|
|
NET sys_flash_wrn LOC = AB6;
|
|
NET sys_flash_ce LOC = W7;
|
|
NET sys_flash_ac97_rstn LOC = AD10;
|
|
NET sys_flash_byten LOC = N22;
|
|
|
|
NET sys_flash_a<*> IOSTANDARD = LVDCI_33;
|
|
NET sys_flash_a<*> SLEW = FAST;
|
|
NET sys_flash_a<*> DRIVE = 8;
|
|
|
|
NET sys_flash_d<*> IOSTANDARD = LVCMOS33;
|
|
NET sys_flash_d<*> DRIVE = 12;
|
|
NET sys_flash_d<*> SLEW = FAST;
|
|
NET sys_flash_d<*> IOBDELAY = NONE;
|
|
NET sys_flash_d<*> PULLDOWN;
|
|
|
|
NET sys_flash_rdn IOSTANDARD = LVDCI_33;
|
|
NET sys_flash_rdn SLEW = FAST;
|
|
NET sys_flash_rdn DRIVE = 8;
|
|
|
|
NET sys_flash_wrn IOSTANDARD = LVDCI_33;
|
|
NET sys_flash_wrn SLEW = FAST;
|
|
NET sys_flash_wrn DRIVE = 8;
|
|
|
|
NET sys_flash_ce IOSTANDARD = LVDCI_33;
|
|
NET sys_flash_ce SLEW = FAST;
|
|
NET sys_flash_ce DRIVE = 8;
|
|
|
|
NET sys_flash_ac97_rstn IOSTANDARD = LVCMOS33;
|
|
NET sys_flash_ac97_rstn DRIVE = 8;
|
|
NET sys_flash_ac97_rstn SLEW = FAST;
|
|
NET sys_flash_ac97_rstn TIG;
|
|
|
|
NET sys_flash_byten IOSTANDARD = LVCMOS33;
|
|
NET sys_flash_byten DRIVE = 8;
|
|
NET sys_flash_byten SLEW = FAST;
|
|
NET sys_flash_byten TIG;
|
|
|
|
# VGA
|
|
NET sys_vga_blue<0> LOC = M21; # VGA_B0
|
|
NET sys_vga_blue<1> LOC = M26; # VGA_B1
|
|
NET sys_vga_blue<2> LOC = L26; # VGA_B2
|
|
NET sys_vga_blue<3> LOC = C5; # VGA_B3
|
|
NET sys_vga_blue<4> LOC = C7; # VGA_B4
|
|
NET sys_vga_blue<5> LOC = B7; # VGA_B5
|
|
NET sys_vga_blue<6> LOC = G8; # VGA_B6
|
|
NET sys_vga_blue<7> LOC = F8; # VGA_B7
|
|
NET sys_vga_blue<0> IOSTANDARD = LVCMOS33;
|
|
NET sys_vga_blue<1> IOSTANDARD = LVCMOS33;
|
|
NET sys_vga_blue<2> IOSTANDARD = LVCMOS33;
|
|
NET sys_vga_blue<*> SLEW = FAST;
|
|
NET sys_vga_blue<*> DRIVE = 8;
|
|
|
|
NET sys_vga_clk LOC = AF8;
|
|
NET sys_vga_clk IOSTANDARD = LVDCI_33;
|
|
NET sys_vga_clk SLEW = FAST;
|
|
NET sys_vga_clk DRIVE = 8;
|
|
|
|
NET sys_vga_green<0> LOC = M22; # VGA_G0
|
|
NET sys_vga_green<1> LOC = M23; # VGA_G1
|
|
NET sys_vga_green<2> LOC = M20; # VGA_G2
|
|
NET sys_vga_green<3> LOC = E4; # VGA_G3
|
|
NET sys_vga_green<4> LOC = D3; # VGA_G4
|
|
NET sys_vga_green<5> LOC = H7; # VGA_G5
|
|
NET sys_vga_green<6> LOC = H8; # VGA_G6
|
|
NET sys_vga_green<7> LOC = C1; # VGA_G7
|
|
NET sys_vga_green<0> IOSTANDARD = LVCMOS33;
|
|
NET sys_vga_green<1> IOSTANDARD = LVCMOS33;
|
|
NET sys_vga_green<2> IOSTANDARD = LVCMOS33;
|
|
NET sys_vga_green<*> SLEW = FAST;
|
|
NET sys_vga_green<*> DRIVE = 8;
|
|
|
|
NET sys_vga_hsync LOC = C10;
|
|
NET sys_vga_hsync SLEW = FAST;
|
|
NET sys_vga_hsync DRIVE = 8;
|
|
#NET sys_vga_hsync IOSTANDARD = LVCMOS33;
|
|
|
|
NET sys_vga_red<0> LOC = N23; #VGA_R0
|
|
NET sys_vga_red<1> LOC = N24; #VGA_R1
|
|
NET sys_vga_red<2> LOC = N25; #VGA_R2
|
|
NET sys_vga_red<3> LOC = C2; #VGA_R3
|
|
NET sys_vga_red<4> LOC = G7; #VGA_R4
|
|
NET sys_vga_red<5> LOC = F7; #VGA_R5
|
|
NET sys_vga_red<6> LOC = E5; #VGA_R6
|
|
NET sys_vga_red<7> LOC = E6; #VGA_R7
|
|
NET sys_vga_red<0> IOSTANDARD = LVCMOS33;
|
|
NET sys_vga_red<1> IOSTANDARD = LVCMOS33;
|
|
NET sys_vga_red<2> IOSTANDARD = LVCMOS33;
|
|
NET sys_vga_red<*> SLEW = FAST;
|
|
NET sys_vga_red<*> DRIVE = 8;
|
|
|
|
NET sys_vga_vsync LOC = A8;
|
|
NET sys_vga_vsync SLEW = FAST;
|
|
NET sys_vga_vsync DRIVE = 8;
|
|
#NET sys_vga_vsync IOSTANDARD = LVCMOS33;
|
|
|
|
NET sys_vga_blank_n LOC = M24;
|
|
NET sys_vga_blank_n SLEW = FAST;
|
|
NET sys_vga_blank_n DRIVE = 8;
|
|
NET sys_vga_blank_n IOSTANDARD = LVCMOS33;
|
|
|
|
NET sys_vga_sync_n LOC = L23;
|
|
NET sys_vga_sync_n SLEW = FAST;
|
|
NET sys_vga_sync_n DRIVE = 8;
|
|
NET sys_vga_sync_n IOSTANDARD = LVCMOS33;
|
|
|
|
#------------------------------------------------------------------------------
|
|
# IO Pad Location Constraints / Properties for AC97 Sound Controller
|
|
#------------------------------------------------------------------------------
|
|
NET "sys_ac97_bit_clk" TNM_NET = "ac97_clk";
|
|
TIMESPEC "TSACBITCLK" = PERIOD "ac97_clk" 80 ns HIGH 50 %;
|
|
|
|
NET sys_ac97_bit_clk LOC = AE10;
|
|
NET sys_ac97_bit_clk IOSTANDARD = LVCMOS33;
|
|
NET sys_ac97_bit_clk PERIOD = 80;
|
|
NET sys_ac97_sdata_in LOC = AD16;
|
|
NET sys_ac97_sdata_in IOSTANDARD = LVCMOS33;
|
|
NET sys_ac97_sdata_out LOC = C8;
|
|
NET sys_ac97_sdata_out SLEW = FAST;
|
|
NET sys_ac97_ssync LOC = D9;
|
|
NET sys_ac97_ssync SLEW = FAST;
|
|
|
|
#------------------------------------------------------------------------------
|
|
# IO Pad Location Constraints / Properties for PS/2 Ports
|
|
#------------------------------------------------------------------------------
|
|
|
|
#Keyboard
|
|
NET sys_ps2_0_clk LOC = D2;
|
|
NET sys_ps2_0_clk SLEW = SLOW;
|
|
NET sys_ps2_0_clk DRIVE = 2;
|
|
NET sys_ps2_0_clk TIG;
|
|
NET sys_ps2_0_data LOC = G9;
|
|
NET sys_ps2_0_data SLEW = SLOW;
|
|
NET sys_ps2_0_data DRIVE = 2;
|
|
NET sys_ps2_0_data TIG;
|
|
|
|
#Mouse
|
|
NET sys_ps2_1_clk LOC = B14;
|
|
NET sys_ps2_1_clk SLEW = SLOW;
|
|
NET sys_ps2_1_clk DRIVE = 2;
|
|
NET sys_ps2_1_clk TIG;
|
|
NET sys_ps2_1_data LOC = C14;
|
|
NET sys_ps2_1_data SLEW = SLOW;
|
|
NET sys_ps2_1_data DRIVE = 2;
|
|
NET sys_ps2_1_data TIG;
|
|
|
|
#------------------------------------------------------------------------------
|
|
# IO Pad Location Constraints / Properties for Ethernet PHY
|
|
#------------------------------------------------------------------------------
|
|
# MDC
|
|
Net sys_phy_mdc LOC = D1;
|
|
Net sys_phy_mdc IOSTANDARD = LVCMOS25;
|
|
|
|
# MDIO
|
|
Net sys_phy_mdio LOC = G4;
|
|
Net sys_phy_mdio IOSTANDARD = LVCMOS25;
|
|
|
|
# /RST
|
|
Net sys_phy_rstn LOC = D10;
|
|
Net sys_phy_rstn TIG;
|
|
|
|
# INT
|
|
Net sys_phy_int LOC = H4;
|
|
Net sys_phy_int TIG;
|
|
|
|
#### Module Ethernet_MAC constraints
|
|
|
|
NET "sys_phy_tx_clk" TNM_NET = "phy_tx_clk";
|
|
TIMESPEC "TS_phy_tx_clk" = PERIOD "phy_tx_clk" 8.0 ns HIGH 50 %;
|
|
|
|
NET "sys_phy_rx_clk" TNM_NET = "phy_rx_clk";
|
|
TIMESPEC "TS_phy_rx_clk" = PERIOD "phy_rx_clk" 8.0 ns HIGH 50 %;
|
|
|
|
Net sys_phy_crs LOC = D5;
|
|
Net sys_phy_col LOC = E3;
|
|
|
|
Net sys_phy_tx_clk LOC=C15;
|
|
Net sys_phy_tx_en LOC = F4;
|
|
Net sys_phy_tx_er LOC=F3;
|
|
Net sys_phy_gtx_clk LOC=G10;
|
|
|
|
Net sys_phy_rx_clk LOC=B15;
|
|
Net sys_phy_rx_dv LOC=A9;
|
|
Net sys_phy_rx_er LOC=B9;
|
|
|
|
Net sys_phy_tx<0> LOC=H1;
|
|
Net sys_phy_tx<1> LOC=H2;
|
|
Net sys_phy_tx<2> LOC=H3;
|
|
Net sys_phy_tx<3> LOC=G1;
|
|
Net sys_phy_tx<4> LOC=G2;
|
|
Net sys_phy_tx<5> LOC=H5;
|
|
Net sys_phy_tx<6> LOC=H6;
|
|
Net sys_phy_tx<7> LOC=G3;
|
|
|
|
Net sys_phy_rx<0> LOC=F1;
|
|
Net sys_phy_rx<1> LOC=E1;
|
|
Net sys_phy_rx<2> LOC=D4;
|
|
Net sys_phy_rx<3> LOC=C4;
|
|
Net sys_phy_rx<4> LOC=B4;
|
|
Net sys_phy_rx<5> LOC=A4;
|
|
Net sys_phy_rx<6> LOC=B3;
|
|
Net sys_phy_rx<7> LOC=A3;
|