jens
be66661fe9
git-svn-id: http://moon:8086/svn/vhdl/trunk@1227 cc03376c-175c-47c8-b038-4cd826a8556b
71 lines
3.3 KiB
VHDL
71 lines
3.3 KiB
VHDL
-------------------------------------------------------------------------
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-- Project: SDRAM controller
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-- This file: User SDRAM component adjustments
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--
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-- Copyright (C) 2007 J. Ahrensfeld
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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-- For questions and ideas, please contact the author at jens@jayfield.org
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--
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--------------------------------------------------------------------------
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library IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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use work.sdram_const.all;
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package sdram_config is
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constant DATA_RATE_FACTOR : positive := 2; -- DDR => twice part data width
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constant PART_DATA_WIDTH : positive := 32; -- External DDR-SDRAM Module data bus width
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constant PART_ADDR_WIDTH : positive := 13; -- number of address lines to DDR-SDRAM Device/Module
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constant PART_BANK_WIDTH : positive := 2; -- Number of BANK address lines of external DDR-SDRAM
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constant PART_ROW_ADDR_WIDTH : positive := 13; --
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constant PART_COL_ADDR_WIDTH : positive := 9; --
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constant PART_DQS_WIDTH : positive := PART_DATA_WIDTH / 8; -- Number of data strobe lines
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constant PART_DM_WIDTH : positive := PART_DATA_WIDTH / 8; -- Number of Data Mask Lines
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constant BUS_DATA_WIDTH : positive := DATA_RATE_FACTOR*PART_DATA_WIDTH; -- DDR => twice part data width
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constant BUS_DM_WIDTH : positive := DATA_RATE_FACTOR*PART_DM_WIDTH; -- DDR => twice part data width
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-- DDR SDRAM Hardware defined constants
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constant BIT_AUTO_PRE : positive := 10; -- bit-position in column address for auto precharge (see Data Sheet)
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constant BIT_PRE_ALL : positive := 10; -- bit-position in column address for precharge all (see Data Sheet)
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constant ENABLE_PRE_ALL : std_logic := '1';
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constant ENABLE_AUTO_PRE : std_logic := '0';
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constant LMR_BL_CURR : natural := LMR_BL2;
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-- DDR-SDR TIMING constants ------------------------------------------------------------------
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-- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh
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constant REFRESH_INTERVAL : real := 7.8125E3; -- [ns]
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-- These values are for your SDRAM part (see datasheet)
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constant TCAS : positive := 2; -- CAS latency [clocks]
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constant TRP : real := 20.0; -- precharge command period [ns]
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constant TRAS : real := 45.0; -- active to precharge delay [ns]
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constant TRFC : real := 75.0; -- auto refresh command period [ns]
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constant TMRD : positive := 2; -- load mode register command cylce time [clocks]
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constant TRCD : real := 20.0; -- active to read or write delay [ns]
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constant TWR : real := 15.0; -- write recovery time [ns]
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constant PWR_UP_WAIT : real := 220.0E3; -- [ns]
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subtype user_tag_t is unsigned(3 downto 0);
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----------------------------------------------------------------------------------------------
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end sdram_config;
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