vhdl/lib/misc/tb_bbfifo.vhd

-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: cpu_embedded using cpu_core and rom
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;

entity tb_bbfifo is
end;

architecture behave of tb_bbfifo is

	-- Number of user data words for simulation
	constant CLK_PERIOD		: time := 10 ns;

	signal rst				: std_logic := '1';  
	signal clk				: std_logic := '1';  
	signal re				: std_logic := '0';  
	signal we				: std_logic := '0';  
	signal dout_vld			: std_logic;  
	signal full				: std_logic;  
	signal half_full		: std_logic;  
	signal din				: unsigned(7 downto 0) := (others => '0');
	signal dout				: unsigned(7 downto 0);
	signal dout_reg			: unsigned(7 downto 0);


begin 
   
inst_bbfifo : entity work.bbfifo
	GENERIC MAP 
	(
		depth_bits	=> 2,
		data_width	=> 8
	)
	PORT MAP
	(
		rst			=> rst,
		clk			=> clk,
		re			=> re,
		we			=> we,
		full		=> full,
		half_full	=> half_full,
		dout_vld	=> dout_vld,
		din			=> din,
		dout		=> dout
	);


CLK_GEN: process
	begin
		wait for CLK_PERIOD/2;
		clk <= not clk;
	end process;

RE_GEN: process
	begin
		wait for 2*CLK_PERIOD;
		wait until rising_edge(clk);
		re <= '1';
		wait until rising_edge(clk);
		re <= '0';
	end process;

PROC_DOUT_REG: process
	begin
		wait until rising_edge(clk);
		if re = '1' and dout_vld = '1' then
			dout_reg <= dout;
		end if;
	end process;

------------------------------------------------------------------------------------------

STIMULUS: process


	begin

		wait for 3*CLK_PERIOD;
		rst <= '0';
		din <= X"10";
		wait until rising_edge(clk) and full = '0';
		we <= '1';
		wait until rising_edge(clk) and full = '0';
		din <= din + 1;
		wait until rising_edge(clk) and full = '0';
		we <= '0';
		wait until rising_edge(clk) and full = '0';
		wait until rising_edge(clk) and full = '0';
		we <= '1';
		din <= din + 1;
		wait until rising_edge(clk) and full = '0';
		din <= din + 1;
		wait until rising_edge(clk) and full = '0';
		we <= '0';
		wait until rising_edge(clk) and full = '0';
		wait until rising_edge(clk) and full = '0';
		wait until rising_edge(clk) and full = '0';
		wait until rising_edge(clk) and full = '0';
		we <= '1';
		din <= din + 1;
		wait until rising_edge(clk) and full = '0';
		we <= '1';
		din <= din + 1;
		wait until rising_edge(clk) and full = '0';
		we <= '1';
		din <= din + 1;
		wait until rising_edge(clk) and full = '0';
		we <= '1';
		din <= din + 1;
		wait until rising_edge(clk) and full = '0';
		we <= '1';
		din <= din + 1;
		wait until rising_edge(clk) and full = '0';
		we <= '1';
		din <= din + 1;
		wait until rising_edge(clk) and full = '0';
		we <= '1';
		din <= din + 1;
		wait until rising_edge(clk) and full = '0';
		we <= '0';

		wait for 30*CLK_PERIOD;
		wait until rising_edge(clk) and full = '0';
		
		we <= '1';
		din <= din + 1;
		wait until rising_edge(clk) and full = '0';
		we <= '1';
		din <= din + 1;
		wait until rising_edge(clk) and full = '0';
		we <= '1';
		din <= din + 1;
		wait until rising_edge(clk) and full = '0';
		we <= '1';
		din <= din + 1;
		wait until rising_edge(clk) and full = '0';
		we <= '1';
		din <= din + 1;
		wait until rising_edge(clk) and full = '0';
		we <= '1';
		din <= din + 1;
		wait until rising_edge(clk) and full = '0';
		we <= '1';
		din <= din + 1;
		wait until rising_edge(clk) and full = '0';
		we <= '0';

		wait; 
	
	end process;
	
end architecture behave;