130 lines
3.2 KiB
VHDL
130 lines
3.2 KiB
VHDL
-------------------------------------------------------------------------
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-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
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-- This file: testbench for embedded cpu with rom
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--
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-- Copyright (C) 2007 J. Ahrensfeld
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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-- For questions and ideas, please contact the author at jens@jayfield.org
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--
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--------------------------------------------------------------------------
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LIBRARY ieee;
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use IEEE.STD_LOGIC_1164.ALL;
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USE ieee.numeric_std.ALL;
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use std.textio.all; -- Imports the standard textio package.
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library work;
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use work.cpu_pkg.all;
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ENTITY tb_cpu_embedded IS
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END tb_cpu_embedded;
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ARCHITECTURE behavior OF tb_cpu_embedded IS
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COMPONENT cpu_embedded
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Port (
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rst : in STD_LOGIC;
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clk : in STD_LOGIC;
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ce : in STD_LOGIC;
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int_in : in STD_LOGIC;
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int_ack : out STD_LOGIC;
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xmem_wait : in STD_LOGIC;
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xmem_we : out STD_LOGIC;
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xmem_re : out STD_LOGIC;
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xmem_din : in unsigned (DMEM_DATA_WIDTH-1 downto 0);
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xmem_dout : out unsigned (DMEM_DATA_WIDTH-1 downto 0);
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xmem_addr : out unsigned (DMEM_ADDR_WIDTH-1 downto 0);
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io_sel : out STD_LOGIC
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);
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END COMPONENT;
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constant CLK_PERIOD : time := 10 ns;
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type sram_t is array (integer range <>) of dmem_data_t;
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signal rst : std_logic := '1';
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signal clk : std_logic := '1';
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signal ce : std_logic := '0';
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signal int_in : std_logic := '0';
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signal int_ack : std_logic;
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signal xmem_wait : std_logic := '0';
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signal xmem_din : dmem_data_t := (others => '-');
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signal xmem_dout : dmem_data_t;
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signal xmem_addr : dmem_addr_t;
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signal xmem_we : std_logic;
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signal xmem_re : std_logic;
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signal io_sel : std_logic;
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signal sram : sram_t(0 to 2**dmem_addr_t'length-1);
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BEGIN
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uut: cpu_embedded
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PORT MAP(
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rst => rst,
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clk => clk,
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ce => ce,
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int_in => int_in,
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int_ack => int_ack,
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xmem_wait => xmem_wait,
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xmem_we => xmem_we,
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xmem_re => xmem_re,
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xmem_din => xmem_din,
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xmem_dout => xmem_dout,
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xmem_addr => xmem_addr,
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io_sel => io_sel
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);
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CLK_GEN: process
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begin
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wait for CLK_PERIOD/2;
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clk <= not clk;
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end process;
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STIMULUS: process
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begin
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wait for 3*CLK_PERIOD;
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rst <= '0';
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wait for 2*CLK_PERIOD;
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wait until rising_edge(clk);
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ce <= '1';
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wait for 1000*CLK_PERIOD;
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assert false report "Test finished" severity error;
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wait;
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end process;
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SRAM_RW: process(rst, clk, xmem_addr, xmem_dout, xmem_we)
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begin
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if (rst = '1') then
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xmem_din <= X"00";
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elsif rising_edge(clk) then
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if io_sel = '0' then
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if xmem_we = '1' then
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sram(to_integer(xmem_addr)) <= xmem_dout;
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end if;
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xmem_din <= to_01(sram(to_integer(xmem_addr)));
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else
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xmem_din <= X"FF";
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end if;
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end if;
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end process;
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END;
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