1182 lines
26 KiB
VHDL
1182 lines
26 KiB
VHDL
-------------------------------------------------------------------------
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-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
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-- This file: loadable ROM
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--
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-- Copyright (C) 2007 J. Ahrensfeld
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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-- For questions and ideas, please contact the author at jens@jayfield.org
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--
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--------------------------------------------------------------------------
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LIBRARY ieee;
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use IEEE.STD_LOGIC_1164.ALL;
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USE ieee.numeric_std.ALL;
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library UNISIM;
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use UNISIM.VComponents.all;
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library work;
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use work.cpu_pkg.all;
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ENTITY irom IS
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Port (
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clk : in STD_LOGIC;
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ce : in STD_LOGIC;
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addr : in inst_addr_t;
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dout : out inst_t
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);
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END irom;
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ARCHITECTURE loadable OF irom IS
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-- JASM_ROM_INSERT_HERE
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-- Assembled from mul8x8.jsm
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type imem_rom_t is array (0 to 1023) of inst_t;
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signal imem_rom : imem_rom_t :=
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(
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"110000" & X"001", -- 0x000: JMP 0x001
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"000011" & X"450", -- 0x001: MOV R00, 0x45
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"000011" & X"F51", -- 0x002: MOV R01, 0xF5
|
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"111011" & X"005", -- 0x003: CALL 0x005
|
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"110000" & X"004", -- 0x004: JMP 0x004
|
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"111100" & X"002", -- 0x005: PUSH R02
|
|
"111100" & X"003", -- 0x006: PUSH R03
|
|
"111100" & X"004", -- 0x007: PUSH R04
|
|
"000010" & X"014", -- 0x008: MOV R04, R01
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|
"000011" & X"001", -- 0x009: MOV R01, 0x00
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|
"000011" & X"002", -- 0x00A: MOV R02, 0x00
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|
"000011" & X"003", -- 0x00B: MOV R03, 0x00
|
|
"001111" & X"014", -- 0x00C: CMP R04, 0x01
|
|
"111001" & X"015", -- 0x00D: JEQ 0x015
|
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"011111" & X"004", -- 0x00E: SHR R04
|
|
"110100" & X"012", -- 0x00F: JNC 0x012
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"010000" & X"002", -- 0x010: ADD R02, R00
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|
"010010" & X"013", -- 0x011: ADDC R03, R01
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|
"011110" & X"000", -- 0x012: SHL R00
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"100010" & X"001", -- 0x013: ROLC R01
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"110000" & X"00C", -- 0x014: JMP 0x00C
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"010000" & X"020", -- 0x015: ADD R00, R02
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"010010" & X"031", -- 0x016: ADDC R01, R03
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"111101" & X"004", -- 0x017: POP R04
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|
"111101" & X"003", -- 0x018: POP R03
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|
"111101" & X"002", -- 0x019: POP R02
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"111110" & X"000", -- 0x01A: RET
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
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"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000",
|
|
"000000" & X"000"
|
|
);
|
|
|
|
signal jtag_ld_clk : STD_LOGIC;
|
|
signal jtag_ld_we : STD_LOGIC;
|
|
signal jtag_ld_addr : inst_addr_t;
|
|
signal jtag_ld_dout : inst_t;
|
|
signal jtag_ld_din : inst_t;
|
|
signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
|
|
signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
|
|
signal user_regi, user_rego : unsigned (31 downto 0);
|
|
constant id : unsigned (31 downto 0) := X"BABE" & X"BEEF";
|
|
|
|
begin
|
|
|
|
--------------------------------------------------------------------------
|
|
-- Virtex-4: JTAG Loader
|
|
--------------------------------------------------------------------------
|
|
i00_BUFG : BUFG
|
|
port map
|
|
(
|
|
O => bs_clk1,
|
|
I => bs_clk0
|
|
);
|
|
|
|
i01_BUFG : BUFG
|
|
port map
|
|
(
|
|
O => bs_update1,
|
|
I => bs_update0
|
|
);
|
|
|
|
BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4
|
|
generic map
|
|
(
|
|
JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
|
|
)
|
|
port map
|
|
(
|
|
CAPTURE => bs_capture, -- CAPTURE output from TAP controller
|
|
DRCK => bs_clk0, -- Data register output for USER functions
|
|
RESET => bs_rst, -- Reset output from TAP controller
|
|
SEL => bs_sel, -- USER active output
|
|
SHIFT => bs_shift, -- SHIFT output from TAP controller
|
|
TDI => bs_tdi, -- TDI output from TAP controller
|
|
UPDATE => bs_update0, -- UPDATE output from TAP controller
|
|
TDO => bs_tdo -- Data input for USER function
|
|
);
|
|
|
|
jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-inst_addr_t'length+1);
|
|
jtag_ld_din <= user_regi(inst_t'length-1 downto 0);
|
|
jtag_ld_clk <= bs_update1;
|
|
jtag_ld_we <= bs_sel;
|
|
|
|
sipo:
|
|
process (bs_rst, bs_clk1, bs_tdi, bs_shift)
|
|
begin
|
|
if bs_rst = '1' then
|
|
user_regi <= (others => '0');
|
|
elsif rising_edge(bs_clk1) then
|
|
if bs_shift = '1' then
|
|
user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
piso:
|
|
process (bs_rst, bs_clk1, bs_shift, user_rego)
|
|
begin
|
|
bs_tdo <= user_rego(0);
|
|
if bs_rst = '1' then
|
|
user_rego <= (others => '0');
|
|
elsif rising_edge(bs_clk1) then
|
|
if bs_shift = '1' then
|
|
user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
|
|
else
|
|
user_rego <= (user_rego'left downto inst_t'length => '0') & jtag_ld_dout;
|
|
-- user_rego <= id;
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
--------------------------------------------------------------------------
|
|
-- ROM Read/Write
|
|
--------------------------------------------------------------------------
|
|
PROM_READ:
|
|
process(clk, ce)
|
|
begin
|
|
if rising_edge(clk) and ce = '1' then
|
|
dout <= imem_rom(to_integer(addr));
|
|
end if;
|
|
end process;
|
|
|
|
PROM_WRITE:
|
|
process(jtag_ld_clk, jtag_ld_we)
|
|
begin
|
|
if rising_edge(jtag_ld_clk) then
|
|
if jtag_ld_we = '1' then
|
|
imem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
|
|
else
|
|
jtag_ld_dout <= imem_rom(to_integer(jtag_ld_addr));
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
--------------------------------------------------------------------------
|
|
end loadable;
|