86 lines
2.2 KiB
VHDL
86 lines
2.2 KiB
VHDL
--------------------------------------------------------------------------
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-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
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-- This file: On-chip RAM
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--
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-- Copyright (C) 2007 J. Ahrensfeld
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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-- For questions and ideas, please contact the author at jens@jayfield.org
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--
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--------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.numeric_std.ALL;
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use work.cpu_pkg.all;
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entity chipram is
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Generic (
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addr_width : integer := 3;
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data_width : integer := 8
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);
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Port (
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clka : in STD_LOGIC;
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clkb : in STD_LOGIC;
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en_a : in STD_LOGIC;
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en_b : in STD_LOGIC;
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we_a : in STD_LOGIC;
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we_b : in STD_LOGIC;
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addr_a : in unsigned (addr_width-1 downto 0);
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addr_b : in unsigned (addr_width-1 downto 0);
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din_a : in unsigned (data_width-1 downto 0);
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din_b : in unsigned (data_width-1 downto 0);
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dout_a : out unsigned (data_width-1 downto 0);
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dout_b : out unsigned (data_width-1 downto 0)
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);
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end chipram;
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architecture Behavioral of chipram is
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constant depth : integer := 2**addr_width;
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type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
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shared variable RAM : RAMtype;
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begin
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process (clka)
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begin
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if clka'event and clka = '1' then
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if en_a = '1' then
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if we_a = '1' then
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RAM(to_integer(addr_a)) := din_a;
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end if;
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dout_a <= RAM(to_integer(addr_a));
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end if;
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end if;
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end process;
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process (clkb)
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begin
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if clkb'event and clkb = '1' then
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if en_b = '1' then
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if we_b = '1' then
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RAM(to_integer(addr_b)) := din_b;
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end if;
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dout_b <= RAM(to_integer(addr_b));
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end if;
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end if;
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end process;
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end Behavioral;
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