jens
026c442fce
Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@939 cc03376c-175c-47c8-b038-4cd826a8556b
151 lines
3.5 KiB
VHDL
151 lines
3.5 KiB
VHDL
-------------------------------------------------------------------------
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-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
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-- This file: testbench for embedded cpu with rom
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--
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-- Copyright (C) 2007 J. Ahrensfeld
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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-- For questions and ideas, please contact the author at jens@jayfield.org
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--
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--------------------------------------------------------------------------
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LIBRARY ieee;
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use IEEE.STD_LOGIC_1164.ALL;
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USE ieee.numeric_std.ALL;
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use std.textio.all; -- Imports the standard textio package.
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library work;
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ENTITY tb_j1 IS
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END tb_j1;
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ARCHITECTURE behavior OF tb_j1 IS
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constant CLK_PERIOD : time := 10 ns;
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-- Inputs
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signal sys_clk_i : std_logic := '0';
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signal sys_rst_i : std_logic := '1';
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signal io_din : unsigned(15 downto 0) := (others => '0');
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signal inst_din : unsigned(15 downto 0) := (others => '0');
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signal data_din : unsigned(15 downto 0) := (others => '0');
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-- Outputs
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signal io_rd : std_logic;
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signal io_wr : std_logic;
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signal io_addr : unsigned(15 downto 0);
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signal io_dout : unsigned(15 downto 0);
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signal data_dout : unsigned(15 downto 0);
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signal inst_addr : unsigned(12 downto 0);
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signal data_addr : unsigned(12 downto 0);
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signal data_we : std_logic;
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signal data_en : std_logic;
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type rom_t is array (integer range <>) of unsigned(15 downto 0);
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signal rom : rom_t(0 to 15) :=
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(
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X"8123", -- 0000
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X"0002", -- 0001
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X"0005", -- 0002
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X"8456", -- 0003
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X"4008", -- 0004
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X"0003", -- 0005
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X"0000", -- 0006
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X"0000", -- 0007
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X"8456", -- 0008
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X"8451", -- 0009
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X"7000", -- 000A
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X"0000", -- 000B
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X"0000", -- 000C
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X"0000", -- 000D
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X"0000", -- 000E
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X"0000" -- 000F
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);
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BEGIN
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-- Instruction rom
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process(sys_clk_i)
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begin
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if rising_edge(sys_clk_i) then
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inst_din <= rom(to_integer(inst_addr(3 downto 0)));
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end if;
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end process;
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uut: entity work.j1
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PORT MAP
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(
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sys_clk_i => sys_clk_i,
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sys_rst_i => sys_rst_i,
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io_din => io_din,
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io_rd => io_rd,
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io_wr => io_wr,
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io_addr => io_addr,
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inst_din => inst_din,
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inst_addr => inst_addr,
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data_addr => data_addr,
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data_we => data_we,
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data_en => data_en,
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data_din => data_din,
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data_dout => data_dout
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);
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inst_ram: entity work.ram_2c_2r_2w
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GENERIC MAP
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(
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addr_width => 13,
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data_width => 16
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)
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PORT MAP(
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clka => sys_clk_i,
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clkb => sys_clk_i,
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en_a => '1',
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en_b => data_en,
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we_a => '0',
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we_b => data_we,
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addr_a => (others => '0'), --inst_addr
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addr_b => data_addr,
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din_a => (others => '0'),
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din_b => data_dout,
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dout_a => open, -- inst_din
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dout_b => data_din
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);
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CLK_GEN: process
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begin
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wait for CLK_PERIOD/2;
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sys_clk_i <= not sys_clk_i;
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end process;
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STIMULUS: process
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begin
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wait for 3*CLK_PERIOD;
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sys_rst_i <= '0';
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wait for 2*CLK_PERIOD;
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wait for 1000*CLK_PERIOD;
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assert false report "Test finished" severity error;
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wait;
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end process;
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end behavior;
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