jens
c5d08ec384
- added UART with FIFO git-svn-id: http://moon:8086/svn/vhdl/trunk@1353 cc03376c-175c-47c8-b038-4cd826a8556b
141 lines
3.1 KiB
VHDL
141 lines
3.1 KiB
VHDL
-- UART Transmitter with integral 16 byte FIFO buffer
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--
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.numeric_std.ALL;
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--
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------------------------------------------------------------------------------------
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--
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-- Main Entity for UART_TX
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--
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entity uart_tx is
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Generic
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(
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fifo_depth_bits : integer := 4
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);
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Port
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(
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rst : in std_logic;
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clk : in std_logic;
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we : in std_logic;
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din : in unsigned(7 downto 0);
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full : out std_logic;
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half_full : out std_logic;
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ser_out : out std_logic;
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tx_complete : out std_logic;
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tx_empty : out std_logic;
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en_16_x_baud : in std_logic
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);
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end uart_tx;
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--
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------------------------------------------------------------------------------------
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--
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-- Start of Main Architecture for UART_TX
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--
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architecture rtl of uart_tx is
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--
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------------------------------------------------------------------------------------
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--
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-- Components used in UART_TX and defined in subsequent entities.
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--
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------------------------------------------------------------------------------------
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--
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-- Constant (K) Compact UART Transmitter
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--
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component juart_tx
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Port
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(
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rst : in std_logic;
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clk : in std_logic;
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din : in unsigned(7 downto 0);
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we : in std_logic;
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en_16_x_baud : in std_logic;
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ser_out : out std_logic;
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Tx_complete : out std_logic
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);
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end component;
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--
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-- 'Bucket Brigade' FIFO
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--
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component bbfifo
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Generic
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(
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depth_bits : integer := 4;
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data_width : integer := 8
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);
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Port
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(
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rst : in std_logic;
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clk : in std_logic;
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we : in std_logic;
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din : in unsigned(7 downto 0);
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full : out std_logic;
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half_full : out std_logic;
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re : in std_logic;
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dout : out unsigned(7 downto 0);
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dout_vld : out std_logic
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);
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end component;
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--
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------------------------------------------------------------------------------------
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--
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-- Signals used in UART_TX
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--
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------------------------------------------------------------------------------------
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--
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signal fifo_data_out : unsigned(7 downto 0);
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signal fifo_data_present : std_logic;
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signal fifo_read : std_logic;
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--
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------------------------------------------------------------------------------------
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--
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-- Start of UART_TX circuit description
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--
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------------------------------------------------------------------------------------
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--
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begin
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tx_complete <= fifo_read;
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tx_empty <= not fifo_data_present;
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juart: juart_tx
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port map
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(
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rst => rst,
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clk => clk,
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din => fifo_data_out,
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we => fifo_data_present,
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en_16_x_baud => en_16_x_baud,
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ser_out => ser_out,
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Tx_complete => fifo_read
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);
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buf: bbfifo
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GENERIC MAP
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(
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depth_bits => fifo_depth_bits,
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data_width => 8
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)
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port map
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(
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clk => clk,
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rst => rst,
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din => din,
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dout => fifo_data_out,
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we => we,
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re => fifo_read,
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full => full,
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half_full => half_full,
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dout_vld => fifo_data_present
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);
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end rtl;
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------------------------------------------------------------------------------------
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--
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-- END OF FILE UART_TX.VHD
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--
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------------------------------------------------------------------------------------
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