vhdl/projects/vga_ctrl/src/tb_vga_ctrl.vhd

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-- Company: 
-- Engineer:
--
-- Create Date:   13:58:47 10/15/2005
-- Design Name:   vga_ctrl_top
-- Module Name:   tb_vga_ctrl.vhd
-- Project Name:  vga_ctrl
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: vga_ctrl_top
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
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LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

use work.vga_types.all;

ENTITY tb_vga_ctrl_vhd IS
END tb_vga_ctrl_vhd;

ARCHITECTURE behavior OF tb_vga_ctrl_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT vga_ctrl_top
    GENERIC
    (
		sys_freq		: real;
		fifo_depth		: integer;
		tsvga			: vga_timespec_t
	);
	PORT
	(
		sys_rstn_in : IN std_logic;
		sys_clk_in : IN std_logic;          
		sys_vga_red : OUT unsigned(7 downto 0);
		sys_vga_green : OUT unsigned(7 downto 0);
		sys_vga_blue : OUT unsigned(7 downto 0);
		sys_vga_blank_n : OUT std_logic;
		sys_vga_sync_n : OUT std_logic;
		sys_vga_hsync : OUT std_logic;
		sys_vga_vsync : OUT std_logic;
		sys_vga_clk : OUT std_logic;
		sys_dip : in unsigned(7 downto 0);
		sys_btn : in unsigned(4 downto 0);
		sys_led : out unsigned(8 downto 0)
	);
	END COMPONENT;

	--Constants
	constant PERIOD : time := 9.9304865938430983118172790466733 ns;

	--Inputs
	SIGNAL sys_rstn_in :  std_logic := '0';
	SIGNAL sys_clk_in :  std_logic := '0';
	SIGNAL sys_color_en :  unsigned(2 downto 0) := (others => '0');
	SIGNAL sys_dip :  unsigned(7 downto 0) := (others => '0');
	SIGNAL sys_btn :  unsigned(4 downto 0) := (others => '0');

	--Outputs
	SIGNAL sys_vga_red :  unsigned(7 downto 0);
	SIGNAL sys_vga_green :  unsigned(7 downto 0);
	SIGNAL sys_vga_blue :  unsigned(7 downto 0);
	SIGNAL sys_vga_blank_n :  std_logic;
	SIGNAL sys_vga_sync_n :  std_logic;
	SIGNAL sys_vga_hsync :  std_logic;
	SIGNAL sys_vga_vsync :  std_logic;
	SIGNAL sys_vga_clk :  std_logic;
	SIGNAL sys_led :  unsigned(8 downto 0);
	constant f_sys : real := 100.0;
	constant f_vga : real := 130.0;
--	SIGNAL test_M : natural := VGA_FREQ_M(f_sys, f_vga);
--	SIGNAL test_D : natural := VGA_FREQ_D(f_sys, f_vga);
	
BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: vga_ctrl_top 
	GENERIC MAP 
	(
		sys_freq	=> f_sys,
		fifo_depth	=> 2048,
		tsvga		=> ts_vga_testbench
	)
	PORT MAP(
		sys_rstn_in => sys_rstn_in,
		sys_clk_in => sys_clk_in,
		sys_vga_red => sys_vga_red,
		sys_vga_green => sys_vga_green,
		sys_vga_blue => sys_vga_blue,
		sys_vga_blank_n => sys_vga_blank_n,
		sys_vga_sync_n => sys_vga_sync_n,
		sys_vga_hsync => sys_vga_hsync,
		sys_vga_vsync => sys_vga_vsync,
		sys_vga_clk => sys_vga_clk,
		sys_dip => sys_dip,
		sys_btn => sys_btn,
		sys_led => sys_led
	);

 	tb_clk : PROCESS
	BEGIN
		sys_clk_in <= not sys_clk_in;
		wait for PERIOD/2;
	END PROCESS;

	tb : PROCESS
	BEGIN

		-- Wait 100 ns for global reset to finish
		wait for 20*PERIOD;
		sys_rstn_in <= '1';

		wait for PERIOD;
		sys_dip <= X"AA";

		wait for PERIOD;
		sys_color_en <= "100";

		wait for 10*PERIOD;
		sys_color_en <= "000";

		-- Wait 100 ns for global reset to finish
		wait for 100 ns;

		-- Place stimulus here

		wait; -- will wait forever
	END PROCESS;

END;