Files
vhdl/lib/VGA_ctrl/sim/tb_vga_frontend64.fdo
T
jens 9485906877 - removed clkgen. VGA-clock generated in TB
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git-svn-id: http://moon:8086/svn/vhdl/trunk@606 cc03376c-175c-47c8-b038-4cd826a8556b
2009-11-05 11:55:53 +00:00

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## NOTE: Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Thu Jul 06 20:49:07 Westeuropäische Sommerzeit 2006
##
vlib work
vcom -explicit -93 "../../misc/utils_pkg.vhd"
vcom -explicit -93 "../../misc/dpram_1w1r.vhd"
vcom -explicit -93 "../../FIFO/src/fifo_ctrl_pkg.vhd"
vcom -explicit -93 "../../FIFO/src/gray_counter.vhd"
vcom -explicit -93 "../../FIFO/src/fifo_async_ctrl.vhd"
vcom -explicit -93 "../../FIFO/src/fifo_async.vhd"
vcom -explicit -93 "../src/fonts/char_rom_c64.vhd"
vcom -explicit -93 "../src/vga_types.vhd"
vcom -explicit -93 "../src/char_gen.vhd"
vcom -explicit -93 "../src/vga_sync.vhd"
vcom -explicit -93 "../src/vga_timing.vhd"
vcom -explicit -93 "../src/vga_backend.vhd"
vcom -explicit -93 "../src/vga_frontend64.vhd"
vcom -explicit -93 "../src/tb_vga_frontend64.vhd"
vsim -t 1ps -lib work tb_vga_frontend64
view wave
do {tb_vga_frontend64.wdo}
view structure
view signals
run 20ms