jens
84e492a1e8
- fixed Xilinx implementation git-svn-id: http://moon:8086/svn/vhdl/trunk@1247 cc03376c-175c-47c8-b038-4cd826a8556b
101 lines
2.1 KiB
VHDL
101 lines
2.1 KiB
VHDL
LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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LIBRARY WORK;
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USE WORK.uart_types.all;
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------------------------------------------------------------------------------------
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ENTITY uart IS
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Port
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(
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clk : in STD_LOGIC;
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rst : in STD_LOGIC;
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we : in STD_LOGIC;
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re : in STD_LOGIC;
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din : in unsigned(7 downto 0);
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dout : out unsigned(7 downto 0);
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ser_rx : in std_logic;
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ser_tx : out std_logic;
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ctrl : in ctrl_t;
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status : out status_t
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);
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END uart;
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ARCHITECTURE rtl OF uart IS
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signal baud_count : unsigned(15 downto 0);
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signal en_16_x_baud : std_logic;
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signal rx_data_present : std_logic;
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signal rx_full : std_logic;
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signal rx_half_full : std_logic;
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signal tx_complete : std_logic;
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signal tx_empty : std_logic;
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signal tx_full : std_logic;
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signal tx_half_full : std_logic;
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begin
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baud_timer:
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process(clk)
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begin
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if rising_edge(CLK_I) then
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if rst = '1' then
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baud_count <= (others => '0');
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elsif baud_count = ctrl.baudrate then
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baud_count <= (others => '0');
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en_16_x_baud <= '1';
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else
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baud_count <= baud_count + 1;
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en_16_x_baud <= '0';
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end if;
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end if;
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end process;
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inst_uart_tx: entity work.uart_tx
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port map
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(
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data_in => std_logic_vector(din),
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write_buffer => we,
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reset_buffer => rst,
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en_16_x_baud => en_16_x_baud,
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serial_out => ser_tx,
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buffer_full => tx_full,
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buffer_half_full => tx_half_full,
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tx_complete => tx_complete,
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tx_empty => tx_empty,
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clk => clk
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);
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inst_uart_rx: entity work.uart_rx
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port map
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(
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serial_in => ser_rx,
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unsigned(data_out) => dout,
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read_buffer => re,
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reset_buffer => rst,
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en_16_x_baud => en_16_x_baud,
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buffer_data_present => rx_data_present,
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buffer_full => rx_full,
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buffer_half_full => rx_half_full,
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clk => clk
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);
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-- Status
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status.rx_present <= rx_data_present;
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status.tx_complete <= tx_complete;
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status.tx_empty <= tx_empty;
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status.tx_full <= tx_full;
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end rtl;
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------------------------------------------------------------------------------------
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--
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-- END OF FILE UART_RX.VHD
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--
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------------------------------------------------------------------------------------
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