jens
8159135dfd
Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@518 cc03376c-175c-47c8-b038-4cd826a8556b
82 lines
4.0 KiB
Plaintext
82 lines
4.0 KiB
Plaintext
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Changes in release 12
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- reworked GCC-toolchain: Valid mips*-elf-binaries are now compiled and linked
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using a single mips*-elf-gcc command.
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To use: Copy $THIS_REALEASE/bsp/toolchain/specs to $MIPS_GCC_PREFIX/lib/gcc/mipsel-elf/$GCC_VERSION/,
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and see bsp/examples/Makefile gcc usage
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GCC-provided crt*-functions are now called without problems.
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In summary: The toolchain is now more compliant to the intentional use of GCC.
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- mips_biu.vhd: Addresses 0xA0000000..0xBFFFFFFF are now un-dcached for memory-mapped I/O,
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which is now compliant to literature.
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- gpio_wb.vhd: Timer reset is now removed. This helps to keep current time in case of CPU reset.
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- new bsp-example source: gunzip
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- updated drawing 'mips_jbus_timing.pdf'
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- added drawing 'memory_map.pdf'
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- moved COP0 from mips_pipeline.vhd to mips_top.vhd. Created new cop-interface for later COPz connection.
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- added I/D-cache info (size and linesize) to upper 16 bits of PrID-Register.
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Example of reading cache info is done in bsp/examples/testbench::PrintCPUinfo()
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- simplified instruction decoder in mips_instr.vhd. Now there are less warnings during synthesis.
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Removed idecode_rom.vhd from project as consequence.
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- added cop0 instructions to invalidate I-cache and D-Cache
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- added copz instructions lwcz and swcz
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- gpio_wb.vhd: added 32 bit timer with interrupt and auto reload
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- added debugger in libsys. New files are mipsdis.c/h and dbg.c/h
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- exception handlers can now be registered to any exception type
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- bugfix: cop0 registers were not written during exception commit. Cop registers now behave like general registers.
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- added pin 'eb' to mips_top.vhd to select CPU-endianess at reset time (eb = 0 : little-endian, eb = 1 : big-endian)
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- Status register bit 'RE'= 1 (bit 25) reverses endianess in user-mode
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- Status register bit 'TS' (TLB Shutdown, bit 21) is tied high to indicate the absence of a MMU.
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- uart_wb.vhd: added interrupt enable
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- Interrupt pending flags (IP) are not anymore masked by Interrupt mask flags (IM) in H/W.
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Masking has to be done in S/W. H/W masking was removed because it isn't MIPS-compliant.
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- added NMI pin (more MIPS compliant). Asserting causes exception. Exception vector is reset (0xBFC00000).
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Using NMI as reset is dangerous because periphery is not reseted.
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Unitialized/unreseted periphery may cause trouble (e.g. firing unwanted interrupts)
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- Bootloader: Startup now invalidates I/D-Caches at boot
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- Bugfix: register bypass with same target register, used for unaligned loads (LWL, LWR), was incorrect. Newlib's memcpy() (MIPS-optimized) uses this.
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Consectutive load instructions without nops (which is legal) using same target register like
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lw $1, 0(mem)
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lwl $1, 1(mem)
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or
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lwl $1, 0(mem)
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lwr $1, 1(mem)
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or similar, lead to incorrect result. Now it'S fixed.
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Changes in release 11
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- bug-fix in mips_pipeline: pc_is_branch is now initialized at reset
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(fixes CPU unrecoverable state after reset)
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- reverted "optimization" in mips_dcache, which behaved buggy during exceptions
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- new example source: test_exception
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- minor changes in libsys
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- added async_port_timing in doc
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- examples/testbench: date set now really works
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Changes in release 10b
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- fixed compiler bug (missing nop after lw) in bootloader,
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which caused exception during boot
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Changes in release 10a
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async_port_wb:
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- added byte enable for async_port
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bootloader.c
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- fixed compiler bug (missing nop after lw)
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mips-core
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- SEL_O lines are also asserted correctly during reads
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tools/romgen
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- TCL-Jtage now compatible with Chipscope 10.1
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mips_sys.c
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- use byte enable for sram and flash
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