jens
deefbcffb3
- use synchronous resets git-svn-id: http://moon:8086/svn/vhdl/trunk@1090 cc03376c-175c-47c8-b038-4cd826a8556b
81 lines
2.1 KiB
VHDL
81 lines
2.1 KiB
VHDL
-------------------------------------------------------------------------
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-- Project: FIFO, generic FIFOs written in VHDL
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-- Release 1
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--
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-- Copyright (C) 2007 J. Ahrensfeld
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--
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-- This library is free software; you can redistribute it and/or
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-- modify it under the terms of the GNU Lesser General Public
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-- License as published by the Free Software Foundation; either
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-- version 2.1 of the License, or (at your option) any later version.
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--
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-- This library is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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-- Lesser General Public License for more details.
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--
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-- You should have received a copy of the GNU Lesser General Public
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-- License along with this library; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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--
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-- For questions and ideas, please contact the author at jens@jayfield.org
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--
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-----------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.numeric_std.ALL;
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LIBRARY WORK;
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USE WORK.FIFO_CTRL_PKG.ALL;
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entity gray_counter is
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Generic (
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width : natural := 3;
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init_value : natural := 0
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);
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Port
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(
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rst : in STD_LOGIC;
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clk : in STD_LOGIC;
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ce : in STD_LOGIC;
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bcnt : out unsigned (width-1 downto 0);
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bnxt : out unsigned (width-1 downto 0);
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gcnt : out unsigned (width-1 downto 0);
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gnxt : out unsigned (width-1 downto 0)
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);
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end gray_counter;
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architecture Behavioral of gray_counter is
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signal cntg : unsigned (width-1 downto 0);
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signal cntb : unsigned (width-1 downto 0);
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signal nxtb : unsigned (width-1 downto 0);
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signal nxtg : unsigned (width-1 downto 0);
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begin
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bnxt <= nxtb;
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gnxt <= nxtg;
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bcnt <= cntb;
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gcnt <= cntg;
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nxtg <= bin2gray(nxtb);
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nxtb <= (cntb + 1) when ce = '1' else cntb;
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process(clk)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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cntb <= to_unsigned(init_value, width);
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cntg <= to_unsigned(init_value, width);
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else
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cntg <= nxtg;
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cntb <= nxtb;
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end if;
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end if;
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end process;
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end Behavioral;
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