jens
097032e4d5
git-svn-id: http://moon:8086/svn/vhdl/trunk@1417 cc03376c-175c-47c8-b038-4cd826a8556b
63 lines
1.3 KiB
VHDL
63 lines
1.3 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 14:01:32 07/10/2006
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-- Design Name:
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-- Module Name: fix_top - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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package my_pkg is
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type my_t is array (integer range <>) of std_logic;
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end package;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use work.my_pkg.all;
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entity top is
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Port ( rst : in STD_LOGIC;
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clk : in STD_LOGIC;
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din : in my_t (0 downto -15);
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dout : out my_t (0 downto -15));
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end top;
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architecture Behavioral of top is
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signal sig1, sig2 : my_t (0 downto -15) := (others => '0');
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begin
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process(clk, rst, din)
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begin
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if (rst = '1') then
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sig1 <= (others => '0');
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sig2 <= (others => '0');
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-- dout <= (others => '0'); -- Commented out due to HDL Advisior's advice
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elsif rising_edge(clk) then
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dout <= sig1;
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sig1 <= din;
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end if;
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end process;
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end Behavioral;
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