353 lines
9.8 KiB
VHDL
353 lines
9.8 KiB
VHDL
-- Constant (K) Compact UART Receiver
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--
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-- Version : 1.10
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-- Version Date : 3rd December 2003
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-- Reason : '--translate' directives changed to '--synthesis translate' directives
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--
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-- Version : 1.00
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-- Version Date : 16th October 2002
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--
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-- Start of design entry : 16th October 2002
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--
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-- Ken Chapman
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-- Xilinx Ltd
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-- Benchmark House
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-- 203 Brooklands Road
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-- Weybridge
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-- Surrey KT13 ORH
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-- United Kingdom
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--
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-- chapman@xilinx.com
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--
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------------------------------------------------------------------------------------
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--
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-- NOTICE:
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--
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-- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other
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-- third parties. By providing this core as one possible implementation of a standard,
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-- Xilinx is making no representation that the provided implementation of this standard
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-- is free from any claims of infringement by any third party. Xilinx expressly
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-- disclaims any warranty with respect to the adequacy of the implementation, including
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-- but not limited to any warranty or representation that the implementation is free
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-- from claims of any third party. Futhermore, Xilinx is providing this core as a
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-- courtesy to you and suggests that you contact all third parties to obtain the
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-- necessary rights to use this implementation.
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--
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------------------------------------------------------------------------------------
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--
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-- Library declarations
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--
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-- The Unisim Library is used to define Xilinx primitives. It is also used during
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-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
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--
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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library unisim;
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use unisim.vcomponents.all;
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--
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------------------------------------------------------------------------------------
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--
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-- Main Entity for KCUART_RX
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--
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entity kcuart_rx is
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Port ( serial_in : in std_logic;
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data_out : out std_logic_vector(7 downto 0);
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data_strobe : out std_logic;
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en_16_x_baud : in std_logic;
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clk : in std_logic);
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end kcuart_rx;
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--
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------------------------------------------------------------------------------------
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--
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-- Start of Main Architecture for KCUART_RX
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--
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architecture low_level_definition of kcuart_rx is
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--
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------------------------------------------------------------------------------------
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--
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------------------------------------------------------------------------------------
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--
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-- Signals used in KCUART_RX
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--
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------------------------------------------------------------------------------------
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--
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signal sync_serial : std_logic;
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signal stop_bit : std_logic;
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signal data_int : std_logic_vector(7 downto 0);
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signal data_delay : std_logic_vector(7 downto 0);
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signal start_delay : std_logic;
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signal start_bit : std_logic;
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signal edge_delay : std_logic;
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signal start_edge : std_logic;
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signal decode_valid_char : std_logic;
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signal valid_char : std_logic;
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signal decode_purge : std_logic;
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signal purge : std_logic;
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signal valid_srl_delay : std_logic_vector(8 downto 0);
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signal valid_reg_delay : std_logic_vector(8 downto 0);
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signal decode_data_strobe : std_logic;
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--
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--
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------------------------------------------------------------------------------------
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--
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-- Attributes to define LUT contents during implementation
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-- The information is repeated in the generic map for functional simulation--
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--
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------------------------------------------------------------------------------------
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--
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attribute INIT : string;
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attribute INIT of start_srl : label is "0000";
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attribute INIT of edge_srl : label is "0000";
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attribute INIT of valid_lut : label is "0040";
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attribute INIT of purge_lut : label is "54";
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attribute INIT of strobe_lut : label is "8";
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--
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------------------------------------------------------------------------------------
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--
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-- Start of KCUART_RX circuit description
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--
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------------------------------------------------------------------------------------
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--
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begin
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-- Synchronise input serial data to system clock
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sync_reg: FD
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port map ( D => serial_in,
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Q => sync_serial,
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C => clk);
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stop_reg: FD
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port map ( D => sync_serial,
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Q => stop_bit,
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C => clk);
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-- Data delays to capture data at 16 time baud rate
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-- Each SRL16E is followed by a flip-flop for best timing
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data_loop: for i in 0 to 7 generate
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begin
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lsbs: if i<7 generate
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--
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attribute INIT : string;
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attribute INIT of delay15_srl : label is "0000";
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--
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begin
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delay15_srl: SRL16E
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--synthesis translate_off
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generic map (INIT => X"0000")
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--synthesis translate_on
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port map( D => data_int(i+1),
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CE => en_16_x_baud,
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CLK => clk,
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A0 => '0',
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A1 => '1',
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A2 => '1',
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A3 => '1',
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Q => data_delay(i) );
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end generate lsbs;
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msb: if i=7 generate
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--
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attribute INIT : string;
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attribute INIT of delay15_srl : label is "0000";
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--
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begin
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delay15_srl: SRL16E
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--synthesis translate_off
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generic map (INIT => X"0000")
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--synthesis translate_on
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port map( D => stop_bit,
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CE => en_16_x_baud,
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CLK => clk,
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A0 => '0',
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A1 => '1',
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A2 => '1',
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A3 => '1',
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Q => data_delay(i) );
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end generate msb;
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data_reg: FDE
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port map ( D => data_delay(i),
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Q => data_int(i),
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CE => en_16_x_baud,
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C => clk);
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end generate data_loop;
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-- Assign internal signals to outputs
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data_out <= data_int;
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-- Data delays to capture start bit at 16 time baud rate
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start_srl: SRL16E
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--synthesis translate_off
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generic map (INIT => X"0000")
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--synthesis translate_on
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port map( D => data_int(0),
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CE => en_16_x_baud,
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CLK => clk,
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A0 => '0',
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A1 => '1',
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A2 => '1',
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A3 => '1',
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Q => start_delay );
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start_reg: FDE
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port map ( D => start_delay,
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Q => start_bit,
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CE => en_16_x_baud,
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C => clk);
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-- Data delays to capture start bit leading edge at 16 time baud rate
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-- Delay ensures data is captured at mid-bit position
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edge_srl: SRL16E
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--synthesis translate_off
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generic map (INIT => X"0000")
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--synthesis translate_on
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port map( D => start_bit,
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CE => en_16_x_baud,
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CLK => clk,
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A0 => '1',
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A1 => '0',
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A2 => '1',
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A3 => '0',
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Q => edge_delay );
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edge_reg: FDE
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port map ( D => edge_delay,
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Q => start_edge,
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CE => en_16_x_baud,
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C => clk);
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-- Detect a valid character
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valid_lut: LUT4
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--synthesis translate_off
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generic map (INIT => X"0040")
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--synthesis translate_on
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port map( I0 => purge,
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I1 => stop_bit,
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I2 => start_edge,
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I3 => edge_delay,
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O => decode_valid_char );
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valid_reg: FDE
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port map ( D => decode_valid_char,
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Q => valid_char,
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CE => en_16_x_baud,
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C => clk);
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-- Purge of data status
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purge_lut: LUT3
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--synthesis translate_off
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generic map (INIT => X"54")
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--synthesis translate_on
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port map( I0 => valid_reg_delay(8),
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I1 => valid_char,
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I2 => purge,
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O => decode_purge );
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purge_reg: FDE
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port map ( D => decode_purge,
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Q => purge,
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CE => en_16_x_baud,
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C => clk);
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-- Delay of valid_char pulse of length equivalent to the time taken
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-- to purge data shift register of all data which has been used.
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-- Requires 9x16 + 8 delays which is achieved by packing of SRL16E with
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-- up to 16 delays and utilising the dedicated flip flop in each stage.
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valid_loop: for i in 0 to 8 generate
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begin
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lsb: if i=0 generate
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--
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attribute INIT : string;
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attribute INIT of delay15_srl : label is "0000";
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--
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begin
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delay15_srl: SRL16E
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--synthesis translate_off
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generic map (INIT => X"0000")
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--synthesis translate_on
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port map( D => valid_char,
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CE => en_16_x_baud,
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CLK => clk,
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A0 => '0',
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A1 => '1',
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A2 => '1',
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A3 => '1',
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Q => valid_srl_delay(i) );
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end generate lsb;
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msbs: if i>0 generate
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--
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attribute INIT : string;
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attribute INIT of delay16_srl : label is "0000";
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--
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begin
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delay16_srl: SRL16E
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--synthesis translate_off
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generic map (INIT => X"0000")
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--synthesis translate_on
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port map( D => valid_reg_delay(i-1),
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CE => en_16_x_baud,
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CLK => clk,
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A0 => '1',
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A1 => '1',
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A2 => '1',
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A3 => '1',
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Q => valid_srl_delay(i) );
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end generate msbs;
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data_reg: FDE
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port map ( D => valid_srl_delay(i),
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Q => valid_reg_delay(i),
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CE => en_16_x_baud,
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C => clk);
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end generate valid_loop;
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-- Form data strobe
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strobe_lut: LUT2
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--synthesis translate_off
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generic map (INIT => X"8")
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--synthesis translate_on
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port map( I0 => valid_char,
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I1 => en_16_x_baud,
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O => decode_data_strobe );
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strobe_reg: FD
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port map ( D => decode_data_strobe,
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Q => data_strobe,
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C => clk);
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end low_level_definition;
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------------------------------------------------------------------------------------
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--
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-- END OF FILE KCUART_RX.VHD
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--
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------------------------------------------------------------------------------------
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