jens
03c23a0271
Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@926 cc03376c-175c-47c8-b038-4cd826a8556b
234 lines
6.8 KiB
VHDL
234 lines
6.8 KiB
VHDL
-------------------------------------------------------------------------
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-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
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-- This file: Testbench for JCPU
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-- also writes 'opc.lst' for JASM-assembler
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--
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-- Copyright (C) 2007 J. Ahrensfeld
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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-- For questions and ideas, please contact the author at jens@jayfield.org
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--
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--------------------------------------------------------------------------
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LIBRARY ieee;
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use IEEE.STD_LOGIC_1164.ALL;
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USE ieee.numeric_std.ALL;
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library work;
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use work.mips_types.all;
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use work.mips_instr.all;
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use work.async_types.all;
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use work.async_defs.all;
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ENTITY tb_mips_sys IS
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END tb_mips_sys;
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ARCHITECTURE behavior OF tb_mips_sys IS
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constant CLK_PERIOD : time := 10 ns;
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constant ICACHE_SIZE : natural := 512; -- words
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constant DCACHE_SIZE : natural := 512; -- words
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constant SRAM_ADDR_WIDTH : integer := 17; -- bits
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constant FLASH_ADDR_WIDTH : integer := 17; -- bits
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signal debug : unsigned(1 downto 0);
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-- Master
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signal nmi : STD_LOGIC := '0';
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signal rst : STD_LOGIC := '1';
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signal clk : STD_LOGIC := '0';
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signal eb : STD_LOGIC := '1';
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signal flash_cs_n : std_logic;
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signal flash_we_n : std_logic;
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signal flash_oe_n : std_logic;
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signal flash_be_n : unsigned(3 downto 0);
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signal sram_cs_n : std_logic;
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signal sram_be_n : unsigned(3 downto 0);
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signal sram_wr_n : std_logic;
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signal sram_oe_n : std_logic;
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signal sram_a : unsigned(SRAM_ADDR_WIDTH-1 downto 0);
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signal sram_d : unsigned(31 downto 0);
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signal flash_a : unsigned(FLASH_ADDR_WIDTH-1 downto 0);
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signal flash_d : unsigned(31 downto 0);
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signal gpo0 : unsigned(31 downto 0);
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signal gpo1 : unsigned(31 downto 0);
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signal gpi0 : unsigned(31 downto 0) := (others => '0');
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signal gpi1 : unsigned(31 downto 0) := (others => '0');
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signal int_timer : std_logic;
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signal int_uart : std_logic;
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signal rx : std_logic := '1';
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signal tx : std_logic;
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type word_array_t is array (natural range <>) of unsigned(31 downto 0);
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signal sram_data : word_array_t(0 to 2**SRAM_ADDR_WIDTH-1);
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signal flash_data : word_array_t(0 to 2**FLASH_ADDR_WIDTH-1);
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BEGIN
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------------------------------------------------------------------
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CLK_GEN: process
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begin
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wait for CLK_PERIOD/2;
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clk <= not clk;
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end process;
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------------------------------------------------------------------
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uut : entity work.mips_sys
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GENERIC MAP
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(
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ICACHE_SIZE => ICACHE_SIZE, -- words
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DCACHE_SIZE => DCACHE_SIZE, -- words
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SRAM_ADDR_WIDTH => SRAM_ADDR_WIDTH,
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FLASH_ADDR_WIDTH => FLASH_ADDR_WIDTH
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)
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PORT MAP
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(
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eb => eb,
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nmi => nmi,
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rst => rst,
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clk => clk,
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flash_cs_n => flash_cs_n,
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flash_oe_n => flash_oe_n,
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flash_we_n => flash_we_n,
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flash_be_n => flash_be_n,
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sram_cs_n => sram_cs_n,
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sram_we_n => sram_wr_n,
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sram_oe_n => sram_oe_n,
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sram_be_n => sram_be_n,
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sram_a => sram_a,
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sram_d => sram_d,
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flash_a => flash_a,
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flash_d => flash_d,
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gpo0 => gpo0,
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gpo1 => gpo1,
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gpi0 => gpi0,
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gpi1 => gpi1,
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rx => rx,
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tx => tx,
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debug => debug
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);
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------------------------------------------------------------------
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SRAM_READ:
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process(sram_a, sram_cs_n, sram_oe_n, sram_be_n)
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begin
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sram_d <= (others => 'Z') after 10 ns;
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if sram_oe_n = '0' then
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if sram_cs_n = '0' then
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if sram_be_n(0) = '0' then
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sram_d(7 downto 0) <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(7 downto 0) after 10 ns;
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end if;
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if sram_be_n(1) = '0' then
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sram_d(15 downto 8) <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(15 downto 8) after 10 ns;
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end if;
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if sram_be_n(2) = '0' then
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sram_d(23 downto 16) <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(23 downto 16) after 10 ns;
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end if;
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if sram_be_n(3) = '0' then
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sram_d(31 downto 24) <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(31 downto 24) after 10 ns;
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end if;
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end if;
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end if;
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end process;
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SRAM_WRITE:
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process(sram_wr_n)
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begin
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if rising_edge(sram_wr_n) then
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if sram_cs_n = '0' then
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if sram_be_n(0) = '0' then
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sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(7 downto 0) <= sram_d(7 downto 0);
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end if;
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if sram_be_n(1) = '0' then
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sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(15 downto 8) <= sram_d(15 downto 8);
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end if;
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if sram_be_n(2) = '0' then
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sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(23 downto 16) <= sram_d(23 downto 16);
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end if;
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if sram_be_n(3) = '0' then
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sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(31 downto 24) <= sram_d(31 downto 24);
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end if;
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end if;
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end if;
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end process;
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------------------------------------------------------------------
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FLASH_READ:
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process(rst, flash_cs_n, flash_oe_n, flash_a)
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type file_t is file of integer;
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file load_flash : file_t open read_mode is "hello.flash.bin";
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variable instr : integer;
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variable index : natural;
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variable temp : signed(31 downto 0);
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constant tpd : time := 25 ns;
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begin
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if rst = '1' then
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index := 0;
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while not endfile(load_flash) loop
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read(load_flash, instr);
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temp := to_signed(instr, word_t'length);
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flash_data(index) <= unsigned(temp);
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index := index + 1;
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end loop;
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else
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flash_d <= (others => 'Z') after tpd;
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index := to_integer(flash_a(FLASH_ADDR_WIDTH-1 downto 2));
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if flash_oe_n = '0' then
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if flash_cs_n = '0' then
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if flash_be_n(0) = '0' then
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flash_d(7 downto 0) <= flash_data(index)(7 downto 0) after tpd;
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end if;
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if flash_be_n(1) = '0' then
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flash_d(15 downto 8) <= flash_data(index)(15 downto 8) after tpd;
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end if;
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if flash_be_n(2) = '0' then
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flash_d(23 downto 16) <= flash_data(index)(23 downto 16) after tpd;
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end if;
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if flash_be_n(3) = '0' then
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flash_d(31 downto 24) <= flash_data(index)(31 downto 24) after tpd;
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end if;
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end if;
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end if;
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end if;
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end process;
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------------------------------------------------------------------
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STIMULUS: process
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begin
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wait for 3*CLK_PERIOD;
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wait until rising_edge(clk);
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rst <= '0';
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wait for 778254*CLK_PERIOD;
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wait until rising_edge(clk);
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nmi <= '0';
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wait for 3000*CLK_PERIOD;
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wait until rising_edge(clk);
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nmi <= '0';
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wait;
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end process;
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END;
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