jens
db9e21023c
- added simulation entities git-svn-id: http://moon:8086/svn/vhdl/trunk@1079 cc03376c-175c-47c8-b038-4cd826a8556b
66 lines
1.7 KiB
VHDL
66 lines
1.7 KiB
VHDL
LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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use std.textio.all; -- Imports the standard textio package.
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--
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------------------------------------------------------------------------------------
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--
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-- Main Entity for UART_TX
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--
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entity uart_tx is
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Port ( data_in : in std_logic_vector(7 downto 0);
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write_buffer : in std_logic;
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reset_buffer : in std_logic;
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en_16_x_baud : in std_logic;
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serial_out : out std_logic;
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buffer_full : out std_logic;
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buffer_half_full : out std_logic;
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tx_complete : out std_logic;
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tx_empty : out std_logic;
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clk : in std_logic);
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end uart_tx;
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------------------------------------------------------------------------------------
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--
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-- Start of UART_TX circuit description
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--
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------------------------------------------------------------------------------------
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--
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ARCHITECTURE behavior OF uart_tx IS
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begin
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serial_out <= '0';
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buffer_full <= '0';
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buffer_half_full <= '0';
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tx_complete <= '1';
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tx_empty <= '1';
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registers_write:
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process(clk)
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file output: text open write_mode is "STD_OUTPUT";
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variable L : line;
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begin
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if rising_edge(clk) then
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if write_buffer = '1' then
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if data_in /= X"0D" then
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write(L, character'val(to_integer(unsigned(data_in))));
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end if;
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if data_in = X"0A" then
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writeline(output, L);
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end if;
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end if;
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end if;
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end process;
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end behavior;
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------------------------------------------------------------------------------------
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--
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-- END OF FILE UART_TX.VHD
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--
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------------------------------------------------------------------------------------
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