vhdl/lib/radio/mix/src/mix_real.vhd

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-- Company: 
-- Engineer:
--
-- Create Date:    12:16:14 10/02/05
-- Design Name:    
-- Module Name:    mix_cpx - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
USE ieee.numeric_std.ALL;

library ieee_proposed;
use ieee_proposed.math_utility_pkg.all;
use ieee_proposed.fixed_pkg.all;

library work;
use work.fixed_util_pkg.all;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mix_real is
Generic
(
	nbits_in		: integer := 12;
	nbits_in_frac	: integer := 12;
	nbits_out		: integer := 12;
	nbits_out_frac	: integer := 12;
	nbits_scale_z	: integer := 0;
	has_in_reg		: boolean := false;
	has_pipe_reg	: boolean := false;
	has_out_reg		: boolean := false;
	rounding		: fixed_round_style_type := fixed_round;
	saturating		: fixed_overflow_style_type := fixed_saturate
);
Port
(
	srst		: in std_logic;
	clk			: in std_logic;
	in_valid	: in std_logic;
	x_re_din	: in sfixed;
	y_re_din	: in sfixed;
	y_im_din	: in sfixed;
	out_valid	: out std_logic;
	z_re_dout	: out sfixed;
	z_im_dout	: out sfixed
);
end mix_real;

architecture Behavioral of mix_real is

constant nbits_prod : integer := nbits_out + nbits_scale_z;
constant nbits_prod_frac : integer := nbits_out_frac + nbits_scale_z;

signal x_re : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
signal y_re, y_im : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
signal p_re_left : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_prod, nbits_prod_frac)'low);
signal p_im_left : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_prod, nbits_prod_frac)'low);
signal valid, p_valid : std_logic;
------------------------------------------------------------
begin


------------------------------------------------------------
	proc_in_reg: process(srst, clk, in_valid, x_re_din, y_re_din, y_im_din)
	begin
		if has_in_reg = true then
			if rising_edge(clk) then
				if srst = '1' then
					x_re <= to_sfixed(0, x_re);
					y_re <= to_sfixed(0, y_re);
					y_im <= to_sfixed(0, y_im);
					valid <= '0';
				else
					valid <= in_valid;
					if in_valid = '1' then
						x_re <= x_re_din;
						y_re <= y_re_din;
						y_im <= y_im_din;
					end if;
				end if;
			end if;
		else
			x_re <= x_re_din;
			y_re <= y_re_din;
			y_im <= y_im_din;
			valid <= in_valid;
		end if;
	end process;

------------------------------------------------------------
	proc_pipe_reg: process(srst, clk, valid, x_re, y_re, y_im)
	variable re_left : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_prod, nbits_prod_frac)'low);
	variable im_left : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_prod, nbits_prod_frac)'low);
	
	begin
		re_left  := resize(x_re * y_re, re_left);
		im_left  := resize(x_re * y_im, im_left);
		if has_pipe_reg = true then
			if rising_edge(clk) then
				if srst = '1' then
					p_re_left  <= to_sfixed(0, p_re_left);
					p_im_left  <= to_sfixed(0, p_im_left);
					p_valid <= '0';
				else
					p_re_left  <= re_left;
					p_im_left  <= im_left;
					p_valid <= valid;
				end if;	
			end if;	
		else	
			p_re_left  <= re_left;
			p_im_left  <= im_left;
			p_valid <= valid;
		end if;	
	end process;
	
------------------------------------------------------------
	proc_out_reg: process(srst, clk, p_valid, p_re_left, p_im_left)
	variable re, im : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
	variable sum_re : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
	variable sum_im : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
	begin
		sum_re := resize(scalb(p_re_left, nbits_scale_z), re, saturating, rounding);
		sum_im := resize(scalb(p_im_left, nbits_scale_z), im, saturating, rounding);
		if has_out_reg = true then
			if rising_edge(clk) then
				if srst = '1' then
					z_re_dout  <= to_sfixed(0, re);
					z_im_dout  <= to_sfixed(0, im);
					out_valid <= '0';
				else
					z_re_dout <= sum_re;
					z_im_dout <= sum_im;
					out_valid <= p_valid;
				end if;	
			end if;	
		else	
			z_re_dout <= re;
			z_im_dout <= im;
			out_valid <= p_valid;
		end if;	
	end process;

------------------------------------------------------------
end Behavioral;